Method of forming fully depleted SIMOX CMOS having electrostatic

Details Method of forming fully depleted SIMOX CMOS having electrostatic Method of forming fully depleted SIMOX CMOS having electrostatic

1998-02-26

2000-09-05

Tran, Andrew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438218, 438412, 438423, H01L 218238, H01L 2126

Patent

active

061141976

ABSTRACT:
The formation of a fully-depleted, ESD protected CMOS device is described. The device is formed on an SOI or SIMOX substrate, over which an oxide pad is grown to a thickness of between 10 and 30 nm. Appropriate ions are implanted into the oxide to adjust the threshold voltage of an ESD transistor. A portion of the top silicon film is thinned to a thickness no greater than 50 nm. The fully depleted CMOS devices are fabricated onto the thinned top silicon film, while the ESD devices are fabricated onto the top silicon film having the original thickness.

REFERENCES:
patent: 5399507 (1995-03-01), Sun
patent: 5773326 (1998-06-01), Gilbert et al.
patent: 5877048 (1999-03-01), Wu
patent: 5894152 (1999-04-01), Jaso et al.
patent: 5923067 (1999-07-01), Voldman
patent: 5952695 (1999-09-01), Ellis-Monaghan et al.
Article entitled, ESD Reliability and Protection Schemes in SOI CMOS Output Buffers by M. Chan, S. Yuen, Z-J Ma, K. Y. Hui, P. K. Ko and C. Hu pulished in the IEEE Transactions on Electron Devices, vol. 42, No. 10, Oct. 1995, pp. 1816-1821.

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