Method of forming floating gate of flash memory

Details Method of forming floating gate of flash memory Method of forming floating gate of flash memory

2002-06-10

2003-11-04

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S264000, C438S266000

Reexamination Certificate

active

06642104

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no.91106950, filed on Apr. 8, 2002.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming the floating gate of a flash memory unit.
2. Description of Related Art
Flash memory is a type of electrical erasable programmable read only memory (EEPROM). Data can be written into or erased from the EEPROM. Most important, however, is that the data is retained even after power supply is cut. Due to versatility of the EEPROM, most personal computer and electronic equipment employ this type of memory. Flash memory is also a type of non-volatile memory (NVM) having the advantages of occupying a small volume, having a fast accessing speed and consuming very little power. Since data inside the flash memory is erased in a block-by block manner, operating speed is exceptionally fast.
FIGS. 1A through 1F
are cross-sectional views showing the progression of steps for forming the floating gate of a conventional flash memory. A substrate
100
having a tunnel oxide layer
102
and a first floating gate layer
104
thereon is provided as shown in FIG.
1
A.
As shown in
FIG. 1B
, the first floating gate layer
104
, the tunnel oxide layer
102
and the substrate
100
are patterned to form an opening
106
in the substrate
100
, a patterned floating gate layer
104
a
and a patterned tunnel oxide layer
102
a.
As shown in
FIG. 1C
, an oxide layer (not shown) is formed over the first floating gate layer
104
a
, filling the opening
106
completely. A chemical-mechanical polishing operation is conducted to remove a portion of the oxide layer and expose the first floating gate layer
104
a
. Hence, a shallow trench isolation region
108
is formed.
As shown in
FIGS. 1D and 1E
, a second floating gate layer
110
is formed over the first floating gate layer
104
a
and the shallow trench isolation region
108
. Thereafter, a patterned photoresist layer
112
is formed over the second floating gate layer
110
. The photoresist layer
112
exposes the second floating gate layer
110
above the shallow trench isolation region
108
.
As shown in
FIG. 1F
, using the photoresist layer
112
as an etching mask, a portion of the second floating gate layer
110
is removed to form a patterned second floating gate layer
110
a
. The patterned first floating gate layer
104
a
and the patterned second floating gate layer
110
a
together constitute a floating gate
114
of a flash memory unit. The floating gate of each flash memory unit is isolated from the others through the shallow trench isolation regions
108
.
As the level of integration for integrated circuits continues to rise, dimensions of each device shrink. Hence, narrower areas have to be set aside for forming the shallow trench isolation regions. Because the conventional method of forming the floating gate of a flash memory relies on simple photolithographic processes, line width and alignment is severely restricted. In other words, if the opening pattern in the photoresist layer
112
is not accurately aligned with the shallow trench isolation regions
108
, the second floating gate layer
110
a
and the first floating gate layer
104
a
may not align with each other. When this is the case, the shallow trench isolation regions
108
may not fully isolate the floating gate
114
of each memory cell from each other.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a method of forming the floating gate of a flash memory unit capable of averting the problem caused by a deviation of floating gate alignment.
A second object of this invention is to provide a method of forming the floating gate of a flash memory unit capable of minimizing the effects due to a reduction of device line width and the limitations of photolithographic process resulting from a reduction in device dimensions.
A third object of this invention is to provide a method of forming the floating gate of a flash memory unit capable of aligning the floating gates and the shallow trench isolation regions together automatically.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming the floating gate of a flash memory unit. A tunnel oxide layer and a first floating gate layer are sequentially formed over a substrate. The first floating gate layer, the tunnel oxide layer and the substrate are patterned to form an opening. A first dielectric layer is formed over the substrate partially filling the opening. A second dielectric layer is formed over the first dielectric layer totally filling the opening. A high etching selectivity ratio exists between the second dielectric layer and the first dielectric layer. A chemical-mechanical polishing operation is conducted to planarize the second dielectric layer and expose the first dielectric layer. Thereafter, a wet etching operation is conducted to remove a portion of the first dielectric layer and expose the first floating gate layer, thereby forming a shallow trench isolation region. The first dielectric material layer surrounds the shallow trench isolation regions. The second dielectric material layer occupies the central portion of the shallow trench isolation regions. Since the second dielectric layer has an etching rate lower than the first dielectric layer, a portion of the second dielectric layer remains after a portion of the first dielectric layer is removed. The retained second dielectric layer rises above the first floating gate layer. A second floating gate layer is formed covering the first dielectric layer, the second dielectric layer and the first floating gate layer. Another chemical-mechanical polishing operation is conducted to planarize the second floating gate layer and expose the second dielectric layer. The first floating gate layer and the second floating gate layer together constitute the floating gate of a flash memory unit. The floating gate of each memory unit is isolated from the others through the shallow trench isolation regions.
The method of forming the floating gate of a flash memory unit according to this invention is capable of preventing alignment deviation resulting from using a conventional photolithographic process to form the floating gate. Moreover, the method of this invention removes one photolithographic processing step and the floating gate is self-aligned. Furthermore, the method is largely unaffected by a narrowing of line width and aligning limitations associated with a photolithographic process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4753901 (1988-06-01), Ellsworth et al.
patent: 6281103 (2001-08-01), Doan
patent: 6294812 (2001-09-01), Ding et al.
patent: 2002/0019113 (2002-02-01), Chung

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