Method of forming embedded DRAM structure

Details Method of forming embedded DRAM structure Method of forming embedded DRAM structure

1999-04-12

2001-05-29

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000

Reexamination Certificate

active

06238967

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing, and more particularly to a method for making an embedded dynamic random access memory (DRAM) cell.
BACKGROUND OF THE INVENTION
In the integrated circuit (IC) industry, manufacturers are currently imbedding dynamic random access memory (DRAM) arrays on the same substrate as CPU cores or other logic devices. This technology is being referred to as embedded DRAM (eDRAM). Embedded DRAM is likely to provide microcontroller (MCU) and other embedded controllers faster access to larger capacities of on-chip memory at a lower cost than that currently available using conventional embedded static random access memory (SRAM) and/or electrically erasable programmable read only memory (EEPROM).
However, the optimal structural needs and process steps needed to form optimal logic devices (e.g., flip-flops, inverters, etc.) is not compatible with the optimal processing and structures of a DRAM cell. For example, logic devices generally benefit from having higher doped source and drain regions, whereas DRAM cells generally benefit from lighter doped source and drain regions. AN issue becomes, how can these two different structures be accomodated in an integrated DRAM and logic process flow to make eDRAM without compromising one of either the DRAM devices or the logic gate devices. In addition, DRAM performance is generally improved by providing shallower source and drain regions whereas logic gates generally benefit by providing at least a portion of the source and drain regions as a deeper doped region. For example, logic gates generally use lightly doped drain (LDD) extensions and highly doped drain (HDD) regions together to improve logic gate performance where such regions in a DRAM device may increase leakage current and/or adversely affect DRAM data retention times.
Further, logic gates generally provide improved performance when containing silicided or salicided source and drain regions. However, salicidation of source and drain regions in a DRAM array may also lead to higher diode leakage within the DRAM cell and poor data retention within the DRAM array. Logic cells generally require the use of interconnect materials that have reduced resistance as opposed to the polysilicon interconnect and plug material that is conventional in DRAM pass transistor contacts. Therefore, tungsten plugs, aluminum plugs, and/or copper interconnects are advantageous within a logic portion of an integrated circuit while tungsten plugs and like metallurgy close to the DRAM pass transistor source and drain regions will generally inhibit the performance of the DRAM cell.
Therefore, a need exists in the industry for a new source and drain configuration for DRAM pass transistors and a new DRAM bit line contact structures that can accommodate the advantageous structures and processes used in the logic portion of the integrated circuit while simultaneously ensuring that DRAM performance is acceptable.


REFERENCES:
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L. Nesbit et al., “A 0.6&mgr;m2 256Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST)”, 1993 IEDM IEEE, Section 26.2.1, pp. 627-630.
S. Crowder et al., “An Embedded DRAM High-Performance 0.18&mgr;m Logic Technology with Copper BEOL”, 1997 IEDM Technical Digest, pp. 45-48.
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J. Y. Lee et al., “Simultaneously Formed Storage Node Contact and Metal Contact Cell (SSMC) for 1 Gb DRAM and Beyond”, 1996 IEDM IEEE, Section 22.2.1, pp. 593-596.
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K.P. Muller et al., “Trench Storage Node Technology for Gigabit DRAM Generations”, 1996 IEDM IEEE, Section 19.4.1, pp. 507-510.
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