Metal working – Method of mechanical manufacture – Electrical device making
Patent
1997-03-14
1999-07-06
Arbes, Carl J.
Metal working
Method of mechanical manufacture
Electrical device making
29840, 156299, 1563073, 156310, 156315, H05K 330
Patent
active
059183640
ABSTRACT:
A method is presented for forming a bumped substrate and for forming an electrical circuit which includes the bumped substrate. The method of forming the bumped substrate includes forming at least one electrically conductive polymer bump on each of a first set of bond pads of the substrate. At least one electrically conductive polymer bump is then formed on each of a second set of the bond pads of the substrate. The circuit is formed by selectively forming an organic protective layer around the bond pads of a second substrate by laser ablation of an organic protective coating polymer bumps on the first and second portions of the bond pads of the first substrate are then contacted with the bond pads of the second substrate, thereby forming the electrical circuit.
REFERENCES:
patent: 2014524 (1935-09-01), Franz
patent: 2774747 (1956-12-01), Wolfson et al.
patent: 3401126 (1968-09-01), Miller et al.
patent: 3429040 (1969-02-01), Miller
patent: 3757075 (1973-09-01), Munt
patent: 3971610 (1976-07-01), Buchoff et al.
patent: 4113981 (1978-09-01), Fujita et al.
patent: 4157932 (1979-06-01), Hirata
patent: 4442966 (1984-04-01), Jourdain et al.
patent: 4554033 (1985-11-01), Dery et al.
patent: 4587038 (1986-05-01), Tamura
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4640981 (1987-02-01), Dery et al.
patent: 4648179 (1987-03-01), Bhattacharyya et al.
patent: 4695404 (1987-09-01), Kwong
patent: 4719140 (1988-01-01), Hara et al.
patent: 4764804 (1988-08-01), Sahara et al.
patent: 4818728 (1989-04-01), Rai et al.
patent: 4840302 (1989-06-01), Gardner et al.
patent: 4872261 (1989-10-01), Sanyal et al.
patent: 4914057 (1990-04-01), Gloton
patent: 4917466 (1990-04-01), Nakamura et al.
patent: 4922321 (1990-05-01), Arai et al.
patent: 4967314 (1990-10-01), Higgins, III
patent: 4985107 (1991-01-01), Conroy et al.
patent: 4991000 (1991-02-01), Bone et al.
patent: 5001302 (1991-03-01), Atsumi
patent: 5068714 (1991-11-01), Seipler
patent: 5074947 (1991-12-01), Estes et al.
patent: 5086558 (1992-02-01), Grube et al.
patent: 5090119 (1992-02-01), Tsuda
patent: 5147210 (1992-09-01), Patterson et al.
patent: 5187020 (1993-02-01), Kwon et al.
patent: 5196371 (1993-03-01), Kulesza et al.
patent: 5218234 (1993-06-01), Thompson et al.
patent: 5270253 (1993-12-01), Arai et al.
patent: 5290423 (1994-03-01), Helber, Jr. et al.
patent: 5329423 (1994-07-01), Scholz
patent: 5508228 (1996-04-01), Nolan et al.
patent: 5674780 (1997-10-01), Lytle et al.
Davis et al., "Solid Logic Technology: Versatile, High-Performance Microelectronics," IBM Journal, vol. 8, pp. 102-114, Apr. 1964.
Totta et al., "SLT Device Metallurgy and its Monolithic Extension," IBM Journal of Research Development, vol. 12, pp. 226-238, May 1969.
Miller, "Controlled Collapse Reflow Chip Joining," IBM Journal of Research Development, vol. 12, pp. 239-250, May 1969.
Cubert et al., "Face-down bonding of monolithic integrated circuit logic arrays," IEEE Electronic Component Conference, pp. 156-167, 1966.
Stein et al., "Some practical considerations in the fabrication of printed glaze resistors and circuits," IEEE Electronic Component Conference, pp. 8-16, 1966.
Scharf et al., "Flip-Component Technology," IEEE Electronic Component Conference, pp. 269-275, 1967.
Miller,"Paste Transfer in the Screening Process," Solid State Technology, vol. 6, pp. 46-52, Jun. 1969.
Ohanian, "Bonding Techniques for Microelectronics," SCP and Solid State Technology, vol. 10, pp. 45-52, Aug. 1967.
Goldman et al., "Lead-Indium for Controlled-Collapse Chip Joining," IEEE Electronic Component Conference, pp. 25-29, 1977.
Utz, "Better Solder Printing with Stencils?" Circuit Manufacturing, vol. 25, No. 9, pp. 43-46, Oct. 1985.
Gabrykewicz et al., "Glob Top Material Selection for Flip Chip Devices," vol. 10, pp. 707-713, 1986.
Gileo, "Direct Chip Interconnect Using Polymer Bonding," 39.sup.th IEEE Electronic Component Conference, pp. 37-44, May 1989.
Leung et al., "Flexible Epoxy Polymer Thick Film Inks," NEPCON EAST, Proceedings, pp. 525-538, Jun. 1987.
Suryanarayana et al., "Flip-Chip Solder Bump Fatigue Life Enhanced by Polymer Encapsulation," IEEE Electronic Component Conference, pp. 338-344, 1990.
Hatada et al., "Application to the Electronic Instrument by Transferred Bump-Tab Technology," 3.sup.rd IEEE CHMT int. Elect. Man. Tech. Symp., pp. 81-86, 1987.
Suhir, "Calculated thermally induced stresses in adhesive bonded and soldered assemblies," Proc. 1986 Int. Symposium on Microelectronics, pp. 383-392, 1986.
Kusagaya et al., "Flip Chip Mounting using Stud Bumps and Adhesives for Encapsulation," International Conference on Multichip Modules, pp. 238-245, 1993.
Hatada et al., "A New LSI Bonding Technology `Micron Bump Bonding Assembly Technology,`" 5.sup.th IEEE CHMT Int. Elect. Man. Tech. Symp., pp. 23-27, 1988.
"Wafer Surface Protection Achieved with Screen Printable Polyimide," Industry News, Semiconductor International, Jun. 1987.
EPO-TEK.RTM. 600 Product Specification, Epoxy Technology, as referred to in Semiconductor International, Jun. 1987.
Kulesza et al., "A Screen-Printable Polyimide Coating for Silicon Wafers," Solid State Technology, Jan. 1988.
Schneider, "Flip-Chip Bonding Offers Packaging Alternative," Hybrid Circuit Technology, pp. 29-31, Mar. 1988.
Kulesza et al., "Solderless Flip-Chip Technology," Hybrid Circuit Technology, Feb. 1992.
Jenczewski, "Stencil Metal Masks for Fine-Pitch Printing," Surface Mount Technology, pp. 45-46, Jun. 1992.
"`Scavenging`for Fine Pitch Quality," Surface Mount Technology, pp. 13-14, Jun. 1992.
EPO-TEK.RTM. H20E-PFC Electrically Conductive Silver Epoxy, Epoxy Technology Product Specification, Sep. 1992.
EPO-TEK.RTM. 688-PFC PFC Silicon Wafer Coating, Epoxy Technology Product Specification, Oct. 1992.
Mandal, "Evaluation of Advanced Microelectronic Fluxless Solder-Bump Contacts for Hybrid Microcircuits," NASA Contractor Report. NAS 8-31496, Jun. 1976.
Szczepanski, "Promising Techniques in On-Chip Assembly of Semiconducting Components and Monolithic Integrated Circuits," NAS 13-33 77A31551, Electronika, pp. 57-61, 1977.
Doo et al., "Semiconductor Chip Cooling Package," IBM Technical Disclosure Bulletin, vol. 20, No. 4, pp. 1440, Sep. 1977.
Kawanobe et al., "Solder Bump Fabrication by Electrochemical Method For Flip Chip Interconnection," Proceedings, 31st-IEEE Electronic Components Conference, Atlanta, GA, 1981.
Delfs, In: Modern Aufbau-Und Verbindungstechniken in der Mikroelektronik Proceedings Seminar, Berlin, 1982.
Ginsberg, "Chip-On-Board Profits From TAB and Flip-Chip Technology," Electronic Packaging and Production, vol. 25, No. 9, p. 140, 1985.
Shumay, "Microjoining for Electronics," Advanced Materials & Processes, vol. 130, No. 5, pp. 38-42, 1986.
Markstein, "TAB Leads as COB Format," Electronic Packaging and Production, vol. 27, No. 10, pp. 46-48, Oct., 1987.
Estes "Fabrication and Assembly Processes for Solderless Flip Chip Assemblies," Proceedings, 1992 International Society for Hybrid Microelectronics Conference, pp. 322-335, 1992.
Estes Richard H.
Kulesza Frank W.
Arbes Carl J.
Lober Theresa A.
Polymer Flip Chip Corporation
LandOfFree
Method of forming electrically conductive polymer interconnects does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming electrically conductive polymer interconnects , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming electrically conductive polymer interconnects will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-891126