Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-30
2002-07-02
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S598000, C438S622000, C438S618000, C438S669000, C438S675000
Reexamination Certificate
active
06413847
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 88119829, filed Nov. 15, 1999.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a semiconductor device. More particularly, the present invention relates to a method of forming a dummy metal pattern for a process of forming a metal interconnect.
2. Description of Related Art
In accordance with the increasing integration in integrated circuits, more than two layers of interconnects has gradually become the standard in many integrated circuit fabrications. In general, a dry etching method is suitable for fabrication of high density semiconductor devices. Accordingly, dry etching becomes the increasingly important for the fabrication of high density semiconductor devices. Dry etching is commonly used to etch a metal layer to form a required metal interconnect pattern.
In order to define a circuity pattern on a silicon wafer, photolithography is performed to transfer the circuit layout pattern to the silicon wafer. The wafer is then transferred into a chamber or a tank to etch out an unnecessary layer of dielectric (or conductive) material which has no photoresist protection above.
FIG. 1A
is a schematic, cross-sectional view showing a metal pattern on a conventional semiconductor substrate. Every metal layer has different spaces between patterns depending on the location of the patterns. As shown in
FIG. 1A
, a wafer
100
includes a region
102
with a dense metal pattern and a region
104
with a sparse metal pattern.
As can be seen from
FIG. 1A
, the metal pattern densities in the above-mentioned regions
102
and
104
are quite different due to the different spaces. If the metal pattern density of the region
104
with a sparse metal pattern is less than a specific density, a dielectric layer which is subsequently formed on the wafer
100
forms a dish-shaped surface. In other words, in cases where the density difference between the regions
102
and
104
is too large, when a dielectric layer is formed on the wafer
100
, the dielectric layer forms a dish-shaped surface. This leads to a different etching rate in the region
102
with a dense metal pattern and in the region
104
with a sparse metal pattern. This is known as a loading effect, and is illustrated in FIG.
1
B.
A dry etching process is a chemical or a chemical/mechanical mixed process, and its reaction rate is related to how dense the material that has to be etched out is. When a metal interconnect is fabricated in a conventional method, the pattern density of metal layers is not uniform and leads to quite different etching rates in the region with dense metal density and in the region with sparse metal density. Thus, disparities in pattern density cause difficulties in etching.
Moreover, another factor that affects an etching process is the thickness of a subsequently formed dielectric material layer (
106
in FIG.
1
B). Since the pattern density of metal layers is not uniform, the dielectric layer forms a dish-like surface having an obviously varying surface height. Thus, the etch stop point is difficult to be detected when etching the dielectric layer, which leads to over or under-etching. Both over and under-etching are not desirable in the integrated circuit manufacturing process.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a method of forming a dummy metal pattern, which can avoid a loading effect while fabricating a metal interconnect.
Another purpose of the invention is to provide a method of forming a dummy metal pattern. The method can enhance reliability of devices and increase yield.
The invention provides a method of forming a dummy metal pattern for a process of forming a metal interconnect. At first, a substrate is provided. The substrate comprises a first region with a dense metal pattern and a second region with a sparse metal pattern. The first region has a higher metal pattern density than that of the second region. Then a metal pattern density of the second region is evaluated. If the metal pattern density of the second region is less than a specific density, then a dummy metal pattern is provided in the second region to make uniform the metal pattern density of the substrate.
The specific density depends on surface shape of a subsequently formed dielectric layer on the substrate. If the metal pattern density of the second region is less than the specific density, the dielectric layer forms a dish-shaped surface. If the metal pattern density of the second region is larger than the specific density, the dielectric layer does not form a dish-shaped surface.
Moreover, the invention provides a method of forming a dummy metal pattern for manufacturing an interconnect pattern. At first, a first dielectric layer is formed on a substrate. A first metal layer is formed on the first dielectric layer. The first metal layer is defined to form a plurality of first metal lines with a first direction wherein the first metal lines are uniform on the substrate. Unnecessary connection between the first metal lines is broken according to the required interconnect pattern. The broken first metal lines remain to form a connected first metal pattern and a first dummy metal pattern so that the substrate has a uniform pattern density. A second dielectric layer is formed on the metal lines and the first dielectric layer. The second dielectric layer is defined, until the first metal lines are exposed, to form a plurality of via holes. A plurality of plugs are formed in the via holes, such that the plugs and the second dielectric layer have the same surface level. A second metal layer is formed on the second dielectric layer and the plugs. The second metal layer is defined to form a plurality of second metal lines with a second direction wherein the second metal lines have a uniform pattern density. Unnecessary connection between the second metal lines is broken according to the interconnect pattern. The broken second metal lines remain to form a connected second metal pattern and a second dummy metal pattern so that the substrate has a uniform pattern density. The connected second metal pattern is electrically connected to the first metal pattern.
Additionally, the invention provides a method for designing a photomask for patterning an interconnect pattern. A metal pattern with uniform pattern density is designed. The metal pattern comprises a first metal pattern with a first direction and uniform pattern density, and a second metal pattern with a second direction and uniform pattern density. The first direction is perpendicular to the second direction. Unnecessary connection between the first metal lines and between the second metal lines is broken according to the interconnect pattern. The broken first metal lines and the broken second metal lines remain to form a connected metal pattern and a dummy metal pattern.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Chang Wei-Yen
Yeh Tsuei-Chi
Duong Khanh
J.C. Patents
Jr. Carl Whitehead
Winbond Electronics Corp.
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