Method of forming dual damascene structure

Details Method of forming dual damascene structure Method of forming dual damascene structure

2000-08-14

2003-03-04

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S725000, C438S745000

Reexamination Certificate

active

06528428

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89115834, filed Aug. 7, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a dual damascene structure. More particularly, the present invention relates to a method of forming a dual damascene opening capable of reducing the degree of interaction between low dielectric constant material and photoresist material.
2. Description of Related Art
Operating speed is often a principle consideration for customers when choosing a particular brand of semiconductor products. At present, major factors that may affect the operating speed of a device include the resistivity of conducting wires and parasitic capacitance of the inter-layer dielectric layer. To reduce wire resistance, low resistance metallic material is often used to form the conducting wires. To improve inter-layer parasitic capacitance, material having a low dielectric constant is frequently employed to form the insulation layer between metallic interconnects.
In general, conventional metallic interconnects are fabricated by forming a metal plug in a dielectric layer followed by depositing aluminum material over the metal plug to form an aluminum wire. Dual damascene technique is a low-cost, highly reliable method of fabricating metallic lines in an integrated circuit. Moreover, the metallic material for forming the-metallic interconnects in a dual damascene structure can be etched without much restriction. Hence, dual damascene techniques are frequently used to form low resistance copper wires for increasing the operating speed of circuit devices. As the level of integration of devices continues to increase, the use of low dielectric constant material to fabricate dual damascene structures is fast becoming the standard in the semiconductor industry.
FIGS. 1A through 1D
are schematic cross-sectional views showing the progression of steps for fabricating a conventional dual damascene structure. As shown in
FIG. 1A
, a substrate
100
having a metallic layer
102
therein is provided. A dielectric layer
104
, an etching stop layer
106
and a dielectric layer
108
are sequentially formed over the substrate
100
. A photoresist layer
110
is next formed over the dielectric layer
108
. Conventional photolithographic technique is applied to pattern the photoresist layer
110
so that location of a via opening is defined.
As shown in
FIG. 1B
, using the photoresist layer
110
as an etching mask, the dielectric layer
108
, the etching stop layer
106
and the dielectric layer
104
are sequentially etched to form a via opening
112
that exposes the metallic layer
102
. The photoresist layer
110
is removed and then another photoresist layer
114
is formed over the substrate
100
. Conventional photolithographic technique is again applied to pattern the photoresist layer
114
so that location of a trench is defined.
As shown in
FIG. 1C
, while using the photoresist layer
114
as an etching mask and the etching stop layer
108
as an etching stop, the dielectric layer
108
is etched to form a trench
116
. In the subsequent step, the photoresist layer
114
is removed and then, as shown in
FIG. 1D
, metal is deposited into the trench
116
and the via opening
112
to form a metallic layer
118
. Ultimately, a dual damascene structure having a cross-sectional profile is formed.
As the level of integration continues to increase, parasitic capacitance that results from the inter-metal dielectric layer is intensified. In particular, low dielectric constant material is frequently employed to form the inter-metal dielectric layer in the manufacturing of deep sub-micron devices so that effects due to resistance-capacitance time delay are reduced. However, common photoresist material is composed of high molecular weight substances and most high dielectric constant material is composed of organic high molecular weight compounds. Consequently, in the photolithographic patterning of the photoresist layers
110
and
114
, organic low dielectric constant material may react chemically with the photoresist material. The resultant products of the reactions may adhere to the surface of the dual damascene contact to form a residue that is impossible to remove in a subsequent cleaning operation. Furthermore, before the dielectric layer
108
is etched to form the trench
116
, photoresist material is often deposited into the via opening
112
to serve as a hard mask so that the metallic layer
102
is protected. This photoresist material often reacts with nearby low dielectric constant material to form a residue. The residue damages the ideal profile of a dual damascene structure and affects the uniformity of a subsequently formed copper seeding layer. A non-linear copper seeding layer often result in the formation of low-quality copper lines.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming a dual damascene structure capable of lowering a parasitic effect by using low dielectric constant material so that highly integrated device circuits are formed. In addition, the method is capable of preventing any chemical reaction between photoresist and dielectric material and thus avoids formation of difficult-to-remove residues on the sidewalls of via openings. Hence, an ideal profile of the dual damascene structure can be preserved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a dual damascene structure. A first dielectric layer, an etching stop layer, a second dielectric layer and a hard mask layer are sequentially formed over a substrate. Photolithographic and etching operations are conducted to remove portions of the hard mask layer, the second dielectric layer, the etching stop layer and the first dielectric layer so that a via opening is formed. A conformal dielectric layer is formed on the surface of the hard mask layer and the interior surface of the via opening. An anisotropic etching operation is carried out to remove the conformal dielectric layer from the surface of the hard mask layer and the bottom of the via opening so that spacers are formed on the sidewalls of the via opening. A patterned photoresist layer is formed over the hard mask layer. Using the patterned photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench. Finally, chemical-mechanical polishing is conducted to remove excess conductive material above the hard mask layer.
In the embodiment of this invention, the spacers serve as a partition that separates the photoresist material from the low dielectric constant material during photoresist coating and developing steps. Consequently, the low dielectric constant first and second dielectric layers are prevented from reacting with photoresist material and the intended dual damascene profile is preserved. The low dielectric constant layer can be a silicon oxide layer formed by low-pressure chemical vapor deposition.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5753967 (1998-05-01), Lin
patent: 6156648 (2000-12-01), Huang
patent: 6211069 (2001-04-01), Hu et al.
patent: 6251774 (2001-06-01), Harada et al.
patent: 6291887 (2001-09-01), Wang et al.
patent: 6297149 (2001-10-01), Stamper
Wolf et al., Silicon Processing for the VLSI Era, 1986, vol. 1, pp. 162-174, 182-195, 520-525, 529-531.

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