Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-12-08
2004-08-10
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S640000, C438S673000, C438S687000, C438S701000, C438S636000
Reexamination Certificate
active
06774031
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for forming dual-damascene structures for metallization in integrated circuit fabrication.
BACKGROUND OF THE INVENTION
With high device speed demands for semiconductor integrated circuits there is a tremendous effort to reduce and minimize the resistor-capacitor (RC) delays that exist in sending signals between or along the metal lines that interconnect integrated circuits. To achieve the required low RC delays copper is used to form the metal interconnects and low k dielectric material is used to provide the isolation between the metal interconnects. Complex integrated circuits typically require multiple levels of copper interconnects separated by multiple levels of low k dielectric insulators. In forming the multiple levels of copper interconnect a damascene technique is most commonly used. In the damascene technique a dielectric (or low K dielectric) layer is first formed over the integrated circuit. A trench is formed in the dielectric layer that is filled with copper. Excess copper is removed using methods such as chemical mechanical polishing (CMP). To connect a copper metal line at one level of interconnect to another copper metal line positioned below, a via is formed in the intervening low k dielectric layer.
In integrated circuits requiring trenches and vias a modified damascene process often referred to as a dual damascene process can be used. In the dual-damascene process a via is first formed in multiple low k dielectric layers. A trench is then formed over the via in the top dielectric layer. The trench and via can then be simultaneously filled with copper to form a copper trench and via. A serious limitation in the use of the dual-damascene process is the formation of ridges and crowns in the low k dielectric layers during the trench etch process. The presence of the ridges and crowns will interfere with the formation of the subsequent copper interconnect trenches and vias causing a deterioration in circuit performance. There is therefore a need for a method to form dual-damascene structures without the formation of ridges and crowns.
SUMMARY OF INVENTION
The instant invention is a method for forming dual damascene structures on integrated circuits. The dual damascene structure is used to form copper structures that are used in the metal interconnects that comprise the integrated circuit. The method comprises forming an etch stop layer over the semiconductor substrate. First and second dielectric layers are formed over the etch stop layer and a hardmask layer is formed over the dielectric layers. A via is formed through both dielectric layers by etching. The via is partially filled with BARC and a trench is partially etched over the via. The BARC is fully or partially removed and the formation of the trench is completed. A liner material is formed in the via and trench and copper is used to fill the trench and via. Excess copper is removed using chemical mechanical polishing.
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Ali Abbas
Newton Kenneth J.
Brady III W. James
McLarty Peter K.
Nguyen Thanh
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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