Method of forming DRAM matrix of basic organizational units each

Details Method of forming DRAM matrix of basic organizational units each Method of forming DRAM matrix of basic organizational units each

1999-06-16

2000-12-05

Mulpuri, Savitri

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

239393, H01L 2170, H01L 218242

Patent

active

061566012

ABSTRACT:
A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.

REFERENCES:
patent: 4651183 (1987-03-01), Lange et al.
patent: 4959698 (1990-09-01), Shinichi
patent: 5014103 (1991-05-01), Ema
patent: 5140389 (1992-08-01), Kimura et al.
patent: 5194752 (1993-03-01), Kumagai et al.
patent: 5686746 (1997-11-01), Iwasa
patent: 5691551 (1997-11-01), Eimori
patent: 5770874 (1998-06-01), Egawa
"GDRAM Cell with Diagonal Bit-Line (DBL Configuration and Edge Operation MOS (EOS) FET" by Shibahar et al 640 IEDM 94, pp. 26.5.1-26.5.4.
"A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256 MBitDRAM." by Eimori et al, IEDM 93-631, pp. 26.3.1 to 26.3.4.

Affiliated with

Also associated with

Rating

Method of forming DRAM matrix of basic organizational units each does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming DRAM matrix of basic organizational units each, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming DRAM matrix of basic organizational units each will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-960891