Method of forming DRAM device having capacitor and DRAM...

Details Method of forming DRAM device having capacitor and DRAM... Method of forming DRAM device having capacitor and DRAM...

2007-08-28

2007-08-28

Landau, Matthew C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000, C257S300000, C257SE27092, C257SE27095, C257SE29346, C257SE21396, C257S296000, C257S068000, C257S071000, C257SE27084, C257SE21646, C257S306000

Reexamination Certificate

active

11301962

ABSTRACT:
In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate are sequentially etched to form a storage node hole. A lower electrode is conformally formed in the storage node hole and on the interlayer dielectric layer. A planarization process is performed to remove a portion of the lower electrode layer that lies on the interlayer dielectric layer and to form a lower electrode in the storage node hole. A dielectric layer and an upper electrode layer are sequentially formed on the lower electrode. The upper electrode layer and the dielectric layer are sequentially patterned.

REFERENCES:
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patent: 10-2004-0059486 (2004-07-01), None

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