Method of forming DRAM cell arrangement

Details Method of forming DRAM cell arrangement Method of forming DRAM cell arrangement

2000-01-13

2002-03-05

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S947000

Reexamination Certificate

active

06352894

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a DRAM cell arrangement and a method for its production. More particularly, the invention relates to a vertically structured DRAM cell arrangement.
2. Description of the Related Art
In DRAM cell arrangements, i.e. memory cell arrangements with dynamic random access, what are known as single transistor memory cells are used almost exclusively. A single transistor memory cell comprises a selection transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electrical charge representing a logical quantity of 0 or 1. By activating the selection transistor via a word line, the information can be read out via a bit line.
Usually, a first source/drain region of the selection transistor is connected to the storage capacitor, and a second source/drain region of the selection transistor is connected to the bit line. A gate electrode of the selection transistor is connected to the word line (cf. e.g. S.M.Sze Semiconductor Devices, AT&T Bell Laboratories, Murray Hill, N.J. 1985, p. 487,
FIG. 18
a
).
Since the memory density increases from generation to generation, the surface of the single transistor memory cell must be reduced from generation to generation. As such, reducing the dimensions of the memory cell is limited by the minimal structural size,
that can be produced in the respective technology. In addition, the memory cell may be altered. Thus, up to the 1 MBit generation, both the selection transistor and the storage capacitor were realized as planar components. Since the 4 MBit memory generation, a further surface reduction has had to occur by means of a three-dimensional arrangement of the selection transistor and storage capacitor.
One option is to design the storage capacitor in a trench instead of in a planar fashion (see K. Yamada, “A deep trenched Capacitor technology for 4 Mbit DRAMs”, Proc. Intern. Electronic Devices and Materials IEDM 85, p. 702). However, the creation of such a buried storage capacitor is expensive. Also, capacitor dielectrics with high dielectricity constants cannot be used, since their deposition is only possible in essentially planar surfaces.
German Patent Document No. 195 19 160 C1 proposes a DRAM cell arrangement in which the storage capacitor is created over the selection transistor, and the bit line is buried in the substrate. Since the storage capacitor is created at a surface of the substrate, capacitor dielectrics with high dielectric constants can be used. Each memory cell has a protuberant semiconductor structure having a first source/drain region. A channel region is positioned underneath the first source/drain region and a second source-drain region is positioned underneath the channel region. The protuberant semiconductor structure is surrounded annularly by a gate electrode.
Semiconductor structures of memory cells are arranged in rows and columns. Neighboring rows of the semiconductor structures are translation-symmetrical in relation to an axis extending parallel to the columns. In order to create word lines in a self-justified fashion, i.e. without using masks that need to be justified, the intervals between semiconductor structures that are arranged along the columns are smaller than intervals between semiconductor structures that are arranged along the rows. The semiconductor structures are surrounded by a grid-shaped depression. The word lines emerge by the deposition and etchback of conductive material in the form of gate electrodes that are situated adjacently along the columns. The buried bit line is created from a doped layer, which is structured in a strip-shaped fashion by trenches filled with insulating material. The trenches are created with the aid of a strip-shaped first mask.
With the aid of a strip-shaped second mask, whose strips extend perpendicular to the trenches, depressions are created between the trenches by the etching of semiconductor material. The depressions do not cut through the doped layer, so as not to cut through the bit line. The semiconductor structures emerge from a layer sequence by the creation of the trenches and the depressions. The depressions are also filled with insulating material. The insulating material is subsequently etched back, the semiconductors are thereby exposed and the grid-shaped depression emerges. Due to the common etching of the insulating material in the depressions and of the insulating material in the trenches, the floor of the grid-shaped depression is flat, which is essential for the self-justified creation of the word lines.
To increase the packing density, the first mask is created in that strips having a width F are first created by a photolithographic process. The strips are widened by the deposition and etchback of material. A distance between neighboring strips of the first mask is thus less than F. The strips of the second mask are created with the width F, by reason of which the above cited conditions regarding the distances between the semiconductor structures are satisfied. The memory cell's surface area is
4
F
2
. The first source/drain region acts as the first capacitor electrode of the storage capacitor. A second capacitor electrode is created by the whole-surface deposition of conductive material over the capacitor dielectric.
In U.S. Pat. No. 4,630,088 it is suggested that the storage capacitor be connected between a first source/drain region of the selection transistor and the bit line. Each memory cell has a protuberant semiconductor structure which is surrounded by a gate electrode annularly. The memory cells are arranged off-set to one another diagonally with respect to a word line direction. The storage capacitor includes the first source/drain region, a part of a whole-surface-deposited capacitor dielectric, and a part of the bit line. The first source/drain region, a channel region and a second source/drain region of the selection transistor are arranged above one another in layers.
SUMMARY OF THE INVENTION
The invention is based on the problem of proposing a DRAM cell arrangement which, given a high packing density, can be produced with a smaller processing outlay than previously available. A production method for such a DRAM cell arrangement is also proposed.
In an inventive DRAM cell arrangement, a semiconductor substrate includes a number of projections arranged in rows and columns. Neighboring rows of the projections are translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each projection has at least one first source/drain region and one channel region of a vertical selection transistor, the channel region being arranged under the first source/drain region. The projection can also have a second source/drain region of the selection transistor. The projection is provided with a gate dielectric at least in the area of the channel region. Each of the projections is surrounded annularly by a gate electrode of the selection transistor. A word line is formed by gate electrodes which neighbor one another along an x-axis parallel to the rows and which are situated adjacently. A first capacitor electrode of the storage capacitor is electrically connected to the first source/drain region. The first capacitor electrode is cut in two by a capacitor dielectric of a second capacitor electrode of the storage capacitor, which is arranged over the first capacitor electrode. The second capacitor electrode is electrically connected to a bit line which extends essentially parallel to the columns. The storage capacitor is connected between the first source/drain region and the bit line. The second source/drain region is buried in the semiconductor substrate.
In order to connect the second source/drain regions of selection transistors to a common potential, it is advantageous to connect at least a few of them to each other.
Since the second source/drain regions are not connected to bit lines, they can be parts of a continuous layer which does not need to be structured. A mask is not necessary for the c

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