Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-09
2003-12-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S255000, C438S258000
Reexamination Certificate
active
06660604
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of forming a dual junction region and a method of forming a transfer transistor using the same, and more particularly to, a dual junction region of a NAND type flash memory device that stably operates in a high voltage bias, and a method of forming a transfer transistor using the same.
2. Description of the Prior Art
In a NAND type flash memory device, program and erase operations are performed through processes in which electrons are injected into a floating gate and the injected electrons are then drawn by means of FN (Fowler/Nordheim) tunneling. The program and erase operations of the flash memory device are performed by applying a high voltage bias of over 20V between two electrodes of a selected memory cell, i.e., a control gate and a substrate.
As described in the above, in order to apply the high voltage bias to the selected memory cell, a transistor for transferring the high voltage bias (hereinafter, called ‘transfer transistor’) is required. In other words, in order to smoothly perform the program and erase operations of the selected memory cell, it is required that the high voltage bias supplied from the outside be transferred to the word lines of the selected memory cell without loss. For this, the transfer transistor is required.
The transfer transistors, known so far, have a dual junction region structure in which a low-concentration doping junction region (hereinafter, called ‘low-concentration junction region’) and a high-concentration doping junction region (hereinafter, called ‘high-concentration junction region’) are formed within a substrate in which wells are formed. A method of manufacturing the dual junction region of the transfer transistor will be described by reference to FIG.
1
through FIG.
3
.
Referring now to
FIG. 1
, wells (not shown) are formed in the semiconductor substrate
102
through a well process. Next, a gate electrode
108
having a structure on which, a gate oxide film
104
and a polysilicon layer
106
are stacked is formed on the semiconductor substrate
102
by means of given deposition process and etch process. A low-concentration junction region
110
is formed in the semiconductor substrate
102
exposed between neighboring gate electrodes
108
by means of a low-concentration doping implantation.
By reference to
FIG. 2
, spacers
112
are formed at both sidewalls of the gate electrode
108
. Next, a high-concentration junction region
114
is formed within the low-concentration junction region
110
by means of a high-concentration doping implantation process using the spacers
112
as an ion implantation mask. Thereby, the dual junction region
116
consisting of the low-concentration junction region
110
and the high-concentration junction region
114
is formed in the semiconductor substrate
102
.
Referring now to
FIG. 3
, an interlayer dielectric film
118
through which a portion of the high-concentration junction region
114
is exposed is formed on the semiconductor substrate
102
. Next, a plug junction region
120
(i.e., region connected to a metal wiring) is formed in the exposed portion of the high-concentration junction region
114
by means of a plug doping implantation process using the interlayer dielectric film
118
as an ion implantation mask. Thereby, the transfer transistor including the dual junction region
116
and the gate electrode
108
is completed.
As described, however, in the transfer transistor having the structure of the dual junction region, if the high voltage bias of over 20V is transferred, a breakdown phenomenon is easily generated between the well within the semiconductor substrate
102
and the dual junction region
116
. Due to this, the high voltage bias to be transferred could not be normally transferred. Generally, it has been reported that the transfer transistor of the dual junction region structure can transfer a high voltage bias of 17V by maximum. However, there are problems that the program and erase operations of the selected memory cell could not be sufficiently efficiently performed and the device characteristic is degraded, under this voltage.
As described above, the breakdown phenomenon between the well of the transfer transistor and the dual junction region of the dual junction region is more easily generated when the difference in the doping concentrations of the regions having difference dopants is large. Also, as the distance between the well and the high-concentration junction region at the dual junction region (see ‘D’ in
FIG. 3
) is close, an avalanche breakdown phenomenon is easily generated. Therefore, the high voltage bias could not be normally transferred. This is because the breakdown voltage between the dual junction region and the well does not endure the high voltage bias of 20V since the well region is diffused into the high-concentration junction region as the distance between the well and the high-concentration junction region is close when the high voltage bias is applied, as indicated by an portion ‘A’ in FIG.
4
. Also, the gate oxide film (see ‘T’ in
FIG. 4
) is usually formed in thickness of 150 through 200Å, which does not also endure the high voltage bias of 20V. Thus, the breakdown phenomenon is generated.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to form a transfer transistor that stably operates in a high voltage bias.
Another object of the present invention is to provide a transfer transistor capable of improving program and erase operations of a memory cell.
In order to accomplish the above object, a method of forming the dual junction region according to the present invention, is characterized in that it comprises the steps of performing a low-concentration doping implantation process for a semiconductor substrate in which several structural layers are formed, thus forming a low-concentration junction region in the semiconductor substrate exposed between the structural layers, depositing an insulating film on the entire structure and then etching the insulating film so that a portion of the low-concentration junction region is exposed, thus forming a contact hole, and performing a high-concentration ion implantation process to form a high-concentration junction region in the portion of the low-concentration junction region exposed through the contact hole.
In order to accomplish another object, a method of forming the transfer transistor according to the present invention, is characterized in that it comprises the steps of forming a gate electrode on a semiconductor substrate in which a well is formed, performing a low-concentration doping implantation process to form a low-concentration junction region in the semiconductor substrate, depositing an insulating film on the entire structure and then etching the insulating film so that a portion of the low-concentration junction region is exposed, thus forming a contact hole, and performing a high-concentration ion implantation process to form a high-concentration junction region in the low-concentration junction region exposed through the contact hole.
REFERENCES:
patent: 5994733 (1999-11-01), Nishioka et al.
patent: 6162668 (2000-12-01), Oda et al.
patent: 6245608 (2001-06-01), Lin et al.
patent: 6245625 (2001-06-01), Gau
patent: 6417081 (2002-07-01), Thurgate
patent: 6512258 (2003-01-01), Maeda
patent: 6562683 (2003-05-01), Wang et al.
Choi Seoung Ouk
Hwang Kyung Pil
Hynix / Semiconductor Inc.
Lindsay Jr. Walter L.
Niebling John F.
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