Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-10-23
2001-06-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06245672
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of integrated circuits, and is more specifically directed to metallization systems used for the conduction of electrical current therein.
For many years, aluminum metallization has been widely used in the fabrication of conductors in conventional integrated circuits. Aluminum metallization, either pure or doped with silicon, copper, or other impurities, has been used in the manufacture of integrated circuits, particularly because of its ease of deposition and ease of patterning and etching, while providing interconnections of reasonable conductivity. However, the use of aluminum necessitates subsequent manufacturing processes to be maintained at relatively low temperatures, given the low melting temperature of aluminum and also its reactivity with other materials, such as silicon. One such temperature-dependent failure mechanism is referred to in the art as “junction spiking”. Junction spiking occurs when aluminum atoms diffuse to such an extent as to short a p-n junction between a doped diffused region at the contact and the underlying well region or substrate.
To prevent junction spiking in modern integrated circuits with very shallow junction depths, barrier metal layers are now commonly placed at contact locations in the integrated circuit. Conventional barrier materials to aluminum include titanium nitride, tantalum nitride, titanium-tungsten alloy, and other refractory materials (including elemental refractory metals, as well as compounds and alloys of the same). These diffusion barriers inhibit the diffusion of aluminum atoms into the underlying silicon at contact locations.
As is fundamental in the integrated circuit art, the chip area required to realize an integrated circuit relates inversely to the manufacturing cost of the integrated circuit. The reduction of manufacturing cost with smaller chip areas is due not only to the larger number of integrated circuits that may be simultaneously fabricated on the same semiconductor wafer, but also due to the increase in theoretical manufacturing yield resulting from smaller chip area (considering that smaller wafer area is rendered useless by a single defect, when chip sizes are smaller). Of course, the ability to manufacture transistors and other elements with smaller feature sizes translates directly into smaller integrated circuit chips for a given function. In addition, by reducing the feature sizes of integrated circuit elements, the resulting integrated circuit also achieves better electrical performance and reduced power dissipation, and may also incorporate a higher degree of functionality. One important dimension in the integrated circuit art is the “pitch” required for the formation of adjacent but electrically isolated metal conductors in an integrated circuit; in some circuit embodiments, the metal pitch may be the limiting factor in shrinking chip area.
The electrical resistance of a given metal conductor is, of course, defined by the reciprocal of the material conductivity, times the ratio of the length of the conductor to its cross-sectional area; in other words, the resistance of an integrated circuit is inversely proportional to its cross-sectional area. This relationship presents a limitation upon the ability to decrease the pitch of metal conductors in an integrated circuit, as smaller metal lines thus necessarily results in higher resistance. Aluminum metallization also suffers from a tendency to “electromigrate”, where aluminum atoms move in response to the electrical current conducted by the metal line; because the electromigration rate depends upon the current density in the conductor, this failure mechanism also limits the extent to which an aluminum metal line may be reduced in cross-sectional area.
Copper has been an attractive material for the realization of integrated circuit conductors for such time, due to its much higher conductivity relative to aluminum. Additionally, copper is more stable, in the electromigration sense, than is aluminum; indeed, the use of copper as a dopant to reduce the rate of electromigration in aluminum metallization is well known in the art. As such, it is contemplated that copper metallization in integrated circuits will enable the reduction in feature size from that possible for aluminum, considering the improvement in conductivity and also the higher current density capability of this material.
However, as is also well known in the art, copper atoms diffuse very rapidly in silicon. For this reason, copper metallization has been avoided in many instances, particularly in metal-oxide-semiconductor (MOS) integrated circuits, as the presence of copper atoms can destroy the integrity of p-n junctions, and thus destroy the functionality of the integrated circuit. This effect of copper is commonly referred to as “poisoning” of junctions. Without adequate barrier materials, especially for MOS integrated circuits, the important benefits of copper metallization can not be achieved.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide high integrity barrier layers for use in conjunction with copper metallization in integrated circuits, and methods of making the same.
It is a further object of the present invention to provide such barrier layers and methods that are well suited for use in integrated circuits having extremely small feature sizes.
It is a further object of the present invention to provide such barrier layers and methods that are suitable for use in integrated circuits having deep aspect ratio contacts and trench structures.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented in a method of fabricating integrated circuits utilizing one or more copper metallization layers that contact silicon and one another through barrier layers. According to the present invention, reactive impurities are introduced at exposed surfaces of refractory metal barrier material, at locations to be contacted by copper metal. Examples of the refractory metal barrier material include elemental titanium or tantalum, silicide compounds thereof, nitride compounds thereof, and the like; examples of the introduced and reacted impurities include elemental carbon, oxygen, and nitrogen. The resulting chemical densification of the barrier layer results in a layer that inhibits the diffusion of copper atoms therethrough.
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patent: 5933758 (1999-08-01), Jain
Aoki, et al., “A degradation-free Cu/HSQ damascene technology using metal mask patterning and post-CMP cleaning by electrolytic ionized water”,Technical Digest, International Eelctron Devices Meeting(Dec. 7, 1997), pp. 31.4.1 through 31.4.4.
Sun, “Process technologies for advanced metallization and interconnect systems”,Technical Digest, International Electron Devices Meeting(Dec. 7, 1997), pp. 31.1.1 through 31.1.4.
Zielinski, et al., “Damascene integration of copper and ultra-low-k xerogel for high performance interconnects”,Technical Digest, International Electron Devices Meeting(Dec. 7, 1997), pp. 31.7.1 through 31.7.3.
Edelstein, et al., Full copper wiring in sub-0.25/spl mu/m CMOS ULSI technology,Technical Digest, International Electron Devices Meeting(Dec. 7, 1997), pp. 31.3.1 through 31.3.4.
Havemann Robert H.
Hong Qi-Zhong
Hsu Wei-Yung
Lu Jiong-Ping
Brady III W. James
Hoang Quoc
McLarty Peter K.
Nelms David
Telecky , Jr. Frederick J.
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