Method of forming dielectric layer with low dielectric constant

Details Method of forming dielectric layer with low dielectric constant Method of forming dielectric layer with low dielectric constant

1999-04-19

2001-11-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S515000

Reexamination Certificate

active

06319850

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a dielectric layer with a low dielectric constant (low-k).
2. Description of Related Art
In the current process of very large scale integration (VLSI), more than two metal layers are fabricated to satisfy the integration requirements. This is called multilevel interconnect. With the increase of integration and the shrinking device size in integrated circuits (IC), metal lines are increasingly closer so that an increasingly serious capacitance effect is induced between the two metal lines. As a result, the crosstalk between conductors and impedance in the circuit structure are increasingly serious so as to increase resistance capacitance time delay. Thus the circuit performance is degraded.
The resistance of conductive lines and a parasitic capacitance are crucial factors to affect the performance. Commonly one resolution is to choose metal material with a low resistance to reduce the resistance between the conductive lines. Another resolution is use of dielectrics with a low dielectric constant (low-k) to reduce the parasitic capacitance.
In the conventional art, a silicon oxide layer is formed between metal lines to serve as a dielectric layer. The method for forming the silicon oxide layer includes high density plasma chemical vapor deposition (HDP-CVD), or plasma enhanced chemical vapor deposition (PECVD) using tetra-ethyl-ortho-silicate (TEOS) as gas source. The dielectric constant of the silicon oxide layer is about 4.1. However, the dielectric constant 4.1 of the dielectric layer is not sufficient for use at the sub-half micro level of fabrication. As a result, a parasitic capacitance induced between conductive lines becomes more serious so as to increase a RC time delay, and reduce the performance.
SUMMARY OF THE INVENTION
The invention provides a method for forming a dielectric layer with a low dielectric constant (low-k). A method for forming a dielectric layer with a low dielectric constant (low-k) is described. A semiconductor substrate is provided. A first dielectric layer is formed on the substrate. A doping step is performed on the dielectric layer. An annealing step is performed and a gas is simultaneously fed so that the first dielectric layer is converted into the low-k dielectric layer. The method further comprises forming a second dielectric layer on the substrate before the first dielectric layer is formed and forming a third dielectric layer on the low-k dielectric layer.
Accordingly, the present invention provides a method for forming a dielectric layer with a low dielectric constant (low-k). The method forms a low-k dielectric layer to reduce a parasitic capacitance induced between conductive lines, efficiently insulate the metal lines and reduce the RC time delay. The invention is simple and economical.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5268311 (1993-12-01), Euen et al.
patent: 5534460 (1996-07-01), Tseng et al.
patent: 5643825 (1997-07-01), Gardner et al.
patent: 6015739 (2000-01-01), Gardner et al.

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