Method of forming conventional complementary MOS transistors...

Details Method of forming conventional complementary MOS transistors... Method of forming conventional complementary MOS transistors...

2006-08-08

2006-08-08

Abraham, Fetsum (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S060000, C438S048000

Reexamination Certificate

active

07087473

ABSTRACT:
A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

REFERENCES:
patent: 2768719 (1998-04-01), None
patent: 10-214906 (1998-08-01), None
patent: 2002-84060 (2002-03-01), None
patent: 2002-314089 (2002-10-01), None
Hoyt, J. L., et al. “Strained Silicon MOSFET Technology” IEDM 2002, pp. 23-26.

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