Method of forming contact structure in a semiconductor device

Details Method of forming contact structure in a semiconductor device Method of forming contact structure in a semiconductor device

2000-08-01

2002-04-23

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S628000, C438S630000, C438S643000, C438S647000, C438S649000, C438S664000

Reexamination Certificate

active

06376368

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, and more particularly, to a method of forming a contact structure of a semiconductor device.
2. Description of the Related Art
With the increase in the integration level or density of semiconductor devices, MOS transistors have become smaller, and the aspect ratios of a contact holes, i.e., the ratio of the lengths of the holes to their widths, increase. When the size (channel length) of a MOS transistor deceases, a short channel effect results such that the electrical characteristics of MOS transistors are degraded. Thus, an impurity layer, such as the source/drain region of a MOS transistor, which is used in highly-integrated semiconductor devices, must be formed to be very thin. However, when the junction depth of an impurity layer is thinly formed, a junction spiking phenomenon occurs in which metal atoms within a metal interconnection, which contacts the impurity layer via a contact hole, penetrate into a semiconductor substrate below the impurity layer.
Accordingly, recent techniques for solving the junction spiking problem by interposing a barrier metal layer and an ohmic metal layer between a metal interconnection and an impurity layer are being prevalently used for highly-integrated semiconductor devices. Also, the barrier metal layer and the ohmic metal layer are being widely used to form a multi-layered metal interconnection. That is, a technique of interposing an ohmic metal layer and a barrier metal layer between a lower metal interconnection exposed by a via hole and an upper metal interconnection which contacts the lower metal interconnection, is being prevalently used.
Also, to increase the integration level of a semiconductor device, the size of a pattern formed in a predetermined region of a semiconductor device, for example, the width of a pattern which defines an impurity layer which is formed in the cell array region or the core region of the semiconductor device, must be as narrow as the width of a pattern depending on the minimum design rule. At this time, when a contact hole is formed on the impurity layer, the bottom area of the contact hole is limited within the width of the impurity layer, thus making it difficult to improve contact resistance. Hence, a process for maximizing the surface area of an impurity layer that is exposed by a contact hole, by forming the contact hole for exposing the impurity layer and also part of an isolation region adjacent to the impurity layer, is being developed.
FIG. 1
is a layout diagram of a metal contact structure which is commonly used in the present invention and in the prior art. Here, a region indicated by reference character a denotes a region in which a first active region
1
a
and a first metal contact hole
3
a
for exposing both the first active region
1
a
and a part of the isolation regions adjacent to the first active region
1
a
are laid out. A region indicated by reference character b denotes a region in which a second active region
1
b
and a second metal contact hole
3
b
for exposing part of the second active region
1
b
are laid out.
FIGS. 2 through 4
are cross-sectional views, taken along line AA′ of
FIG. 1
, for illustrating a conventional method of forming a metal contact structure. Here, a portion indicated by reference character a denotes a portion in which the first metal contact hole
3
a
of
FIG. 1
is formed, and a portion indicated by reference character b denotes a portion in which the second metal contact hole
3
b
of
FIG. 1
is formed.
Referring to
FIG. 2
, an isolation layer
13
for defining an active region is formed on a predetermined region of the semiconductor substrate
11
. The isolation layer
13
is formed by forming a trench through etching of the predetermined region of the semiconductor substrate
11
and filling the trench with an insulating layer such as a silicon oxide layer. First and second impurity layers
15
a
and
15
b
are formed by implanting impurities having a different conductivity type than the conductivity type of the semiconductor substrate
11
, such as N-type or P-type impurities, into the surface of the active region between adjacent isolation layers
13
. The first impurity layer
15
a
is narrower than the second impurity layer
15
b
. An inter;-dielectric layer
17
is formed on the entire surface of the semiconductor substrate
11
on which the first and second impurity layers
15
a
and
15
b
have been formed.
Referring to
FIG. 3
, first and second metal contact holes H
1
and H
2
for exposing the first and second impurity layers
15
a
and
15
b
, respectively, are formed by patterning the inter-dielectric layer
17
. The first metal contact hole H
1
is formed so that a portion of the isolation layer
13
adjacent to the first impurity layer
15
a
is exposed, in order to maximize the area of the first impurity layer
15
a
that is exposed. At this time, the isolation layer
13
is also etched, resulting in a recessed region which exposes the sidewalls of the first impurity layer
15
a
. When over-etching is performed to pattern the first and second metal contact holes H
1
and H
2
, recessed regions, which expose the sidewalls of the first impurity layer
15
a
and also the semiconductor substrate
11
portion below the first impurity layer
15
a
, may be formed.
Next, an ohmic metal layer
19
and a barrier metal layer
21
are sequentially formed on the entire surface of the semiconductor substrate on which the first and second metal contact holes H
1
and H
2
have been formed. The ohmic metal layer
19
and the barrier metal layer
21
are formed of titanium and titanium nitride, respectively. A sputtering process is generally used to form the ohmic metal layer
19
and the barrier metal layer
21
. The ohmic metal layer
19
portion and the barrier metal layer
21
portion deposited on the bottoms and sidewalls of the first and second metal contact holes H
1
and H
2
, respectively, are thinner than those deposited on the upper surface of the inter-dielectric layer
17
, due to the characteristics of the sputtering process. In particular, as the aspect ratios of the first and second metal contact holes H
1
and H
2
increase, the step coverages of the ohmic metal layer
19
and the barrier metal layer
21
formed by the sputtering process become poor. Thus, when the ohmic metal layer
19
and the barrier metal layer
21
are formed after a metal contact hole having a high aspect ratio is formed, the ohmic metal layer
19
portion and the barrier metal layer
21
portion at the lower corners C
1
and C
2
of the first and second metal contact holes H
1
and H
2
are very thin, as shown in FIG.
3
. The ohmic metal layer
19
portions at the lower corners C
1
of the first metal contact hole H
1
contact the sidewalls of the first impurity layer
15
a
, and also may directly contact the semiconductor substrate
11
.
Referring to
FIG. 4
, the resultant structure on which the ohmic metal layer
19
and the barrier metal layer
21
have been formed is thermally treated to react the ohmic metal layer
19
with the impurity layers
15
a
and
15
b
. Thus, first and second metal silicide Layers
19
a
and
19
b
are formed on the first and second impurity layers
15
a
and
15
b
, respectively. Here, the edges of the first metal silicide layer
19
a
formed on the first impurity layer
15
a
can make contact with the semiconductor substrate
11
as shown in FIG.
4
. Consequently, when a reverse bias is applied between the first impurity layer
15
a
and the semiconductor substrate
11
, the amount of junction leakage current significantly increases on account of the first metal silicide layer
19
a
, causing malfunction of the device.
Next, a metal layer
23
for filling the first and second contact holes H
1
and H
2
, for example, a tungsten layer, is formed on the entire surface of the semiconductor substrate on which the first and second metal silicide layers
19
a
and
19
b
have been f

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