Method of forming contact plugs

Details Method of forming contact plugs Method of forming contact plugs

2002-02-01

2003-04-15

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S587000, C438S624000, C438S625000, C438S637000, C438S645000, C438S672000, C257S296000, C257S906000

Reexamination Certificate

active

06548394

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor process and, more particularly, to a method of forming a bitline contact plug.
2. Description of the Related Art
When manufacturing memory products such as trench-type DRAM, stacked-type DRAM and FLASH memory, in order to reduce the size of a chip, the conventional semiconductor process uses self-aligned contact (SAC) technology to define a reduced distance between two adjacent gate conducting structures.
FIGS. 1A
to
1
H are sectional diagrams showing a conventional method of forming contact plugs using SAC process. As shown in
FIG. 1A
, a P-type silicon substrate
10
is provided with a plurality of shallow trench isolation (STI) regions
12
in the substrate
10
for isolating adjacent active areas (AA), a gate insulating layer
14
formed on the substrate
10
, a plurality of gate conducting structures
161
,
162
,
163
and
164
patterned on the gate insulating layer
14
, and a plurality of N
−
-type ion implantation regions
20
formed in the substrate
10
and at lateral regions of the gate conducting structures
161
-
164
. Each of the gate conducting structures
161
-
164
is stacked by a polysilicon layer
17
, a tungsten silicide layer
18
, and a silicon nitride cap layer
19
. As shown in
FIG. 1B
, a silicon oxide spacer
22
is grown on the sidewalls of the polysilicon layer
17
and the tungsten silicide layer
18
, and then a silicon nitride spacer
24
is formed on the sidewalls of the gate conducting structures
161
-
164
. Next, using ion implantation with the gate conducting structures
161
-
164
and the silicon nitride spacer
24
as the mask, an N
+
-type ion implantation region
26
is formed in the exposed N
−
-type ion implantation region
20
. Thereby, the N
+
-type ion implantation region
26
serves as a source/drain region, and the remaining N
−
-type ion implantation region
20
serves as a lightly doped drain (LDD) structure.
As shown in
FIG. 1C
, a SiON liner
28
is deposited on the entire surface of the substrate
10
, and then an inter-layered dielectric (ILD) layer
30
with a planarized surface is formed on the SiON liner
28
to fill the gaps between adjacent gate conducting structures
161
-
164
by deposition and chemical mechanical polishing (CMP). Preferably, the ILD layer
30
is BPSG, HDP oxide, TEOS. Next, as shown in
FIG. 1D
, using a first photoresist layer
31
with a pattern of the bitline contact plug formed as the mask, the ILD layer
30
and the SiON liner
28
formed between the two gate conducting structures
162
and
163
are removed to expose the N
+
-type ion implantation region
26
, thus forms a bitline contact hole
32
. Thereafter, as shown in
FIG. 1E
, after removing the first photoresist layer
31
, a first conductive layer is deposited to fill the bitline contact hole
32
and then etched back to a predetermined height within the bitline contact hole
32
, thus the first conductive layer remaining in the bitline contact hole
32
serves as a bitline contact plug
34
.
As shown in
FIG. 1F
, using a second photoresist layer
35
with a pattern of interconnection contact plugs as the mask, part of the ILD layer
30
, the SiON liner
28
and the silicon nitride cap layer
19
is removed to form a first interconnection contact hole
36
and a second interconnection contact hole
38
. The first interconnection contact hole
36
is formed over the first gate conducting structure
161
to expose the top of the tungsten silicide layer
18
. The second interconnection contact hole
38
is formed outside the gate conducting structure
164
to expose the N
+
-type ion implantation region
26
. Next, as shown in
FIG. 1G
, after removing the second photoresist layer
35
, a third photoresist layer
39
with a pattern of interconnections is employed as a mask to etch predetermined regions of the ILD layer
30
. Finally, as shown in
FIG. 1H
, a second conductive layer
40
is deposited on the entire surface of the substrate
10
to fill the first interconnection contact hole
36
and the second interconnection contact hole
38
. Then, CMP is employed to level off the top of the second conductive layer
40
and the top of the ILD layer
30
. Therefore, the second conductive layer
40
formed on the ILD layer
30
serves as an interconnection structure
40
a,
and the second conductive layer
40
formed in the first/second interconnection contact hole
36
/
38
serves as a first/second interconnection contact plug
40
b.
However, the above-described SAC process has disadvantages as listed below. First, when the STI region
12
is very large or a problem of step height between AA and STI causes misalignment during photolithography or CMP cannot provide the ILD layer
30
with an appropriate thickness and superior flatness, the etched profile of the contact hole would be affected, and it would cause problems of the interconnection structure, such as a short circuit between bitline and wordline or a blind window in the bitline contact hole
32
. Second, since the etching selectivity from the ILD layer
30
to the SiON liner
28
is not large enough to provide etching stop capability during the formation of the bitline contact hole
32
, seams are probably formed in the STI region
12
to cause junction leakage between the bitline contact plug
34
and the substrate
10
. Third, the silicon nitride cap layer
19
requires a thick thickness in the SAC process, thus thermal budget is increased and electrical properties, such as V
t
, I
dsat
, I
off
, are worsened. Fourth, if the SAC process is applied to manufacture a device of a further reduced size, the problems encountered in photolithography becomes more difficult. Fifth, the materials used for the cap layer
19
and the spacer
24
are limited to SiN or SiON, resulting in worsening the leakage problem in the polysilicon layer
17
.
SUMMARY OF THE INVENTION
The present invention is a method of forming contact plugs to solve the above-mentioned problems.
The method of forming contact plugs is used on a semiconductor substrate with at least four adjacent gate conducting structures, wherein a second gate conducting structure and a third gate conducting structure are formed within an active area. First, the gap between the second gate conducting structure and the third gate conducting structure is filled with a first conductive layer. Then, an inter-layered dielectric (ILD) layer with a planarized surface is formed on the entire surface of the substrate to cover the first conductive layer. Next, a bitline contact hole is formed in the ILD layer to expose the first conductive layer. Thereafter, the bitline contact hole is filled with a second conductive layer to serve as a bitline contact plug.
Accordingly, it is a principle object of the invention to prevent the formation of the bitline contact hole from poor etching profile, short circuits in the interconnection structure and blind window.
It is another object of the invention to prevent the formation of seams in the STI region.
Yet another object of the invention is to provide a stable contact resistance between the bitline contact plug and the substrate.
It is a further object of the invention to reduce thermal budget and promote electrical properties of the product.
Still another object of the invention is to be applied to manufacture a device of a further reduced size without encountering problems in photolithography.
Another object of the invention is to increases the selectiveness of using materials.


REFERENCES:
patent: 6090697 (2000-07-01), Xing et al.
patent: 6121128 (2000-09-01), Hakey et al.

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