Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-09-29
2004-06-29
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S700000, C438S714000
Reexamination Certificate
active
06756315
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the manufacture of semiconductor devices and, more particularly, to a method of forming a contact hole to an active or electrically functional region of a semiconductor device.
2. Discussion of the Background
During the semiconductor fabrication process, multiple conductive layers such as metal and/or polysilicon layers are often deposited on a semiconductor wafer or substrate, which is typically made of silicon. Conductive layers are sometimes separated from each other by an insulating dielectric layer including one or more materials such as silicon dioxide and/or silicon nitride. These conductive layers are selectively connected or “wired” together to allow for conduction of electricity in a desired pattern.
Semiconductor devices perform their functions only after they have been interconnected in a prescribed manner. To accomplish this, typically contact openings or holes are opened (e.g., etched) in the dielectric layers. Electrically conductive materials (e.g., metals) later deposited into these holes form “contacts,” “plugs” or “vias” (hereinafter referred to as “contacts”) that contact the source, drain and gate regions of transistors to overlying conductors, for example.
The formation of contact holes in the oxide that covers the substrate surface is a key step in the fabrication of interconnect structures. The process typically starts by etching the oxide through the openings that are patterned on a mask that is formed on the oxide layer. Usually, a photoresist serves as a mask, as is well known in the art. Subsequently, the photoresist is removed.
Oxide materials are principally used for electrically insulating layers. “Oxide” is a somewhat generic term used for silica, particularly silicon dioxide (SiO
2
). Because of the limits set by dielectric breakdown, the thickness of the oxide layers cannot be reduced to much below 0.5 to 1.0 micrometers. The minimum feature size of contact holes penetrating the oxide layer, however, is being pushed to below 0.1 micrometers. The result is that the holes etched in the oxide must be highly vertical and must have a high aspect ratio (i.e., ratio of the depth of the hole to the minimum width of the hole).
During formation of the contact openings, contaminants and impurities often form on the silicon surface of the wafer. Sometimes, because of the increasingly small size of the holes and/or the high aspect ratio of the holes, it is difficult to clean the bottoms of the holes subsequent to etching. The presence of contaminants and impurities contributes significantly to high contact resistance because the contaminants and impurities act as insulators between the substrate surface and the metal that is to be later deposited into the hole. Moreover, for a given substrate and a given material contacting the substrate, the contact resistance increases as a function of the contact area. The area available for forming self-aligned contacts is generally limited by the distance between adjacent transistor gates, which is minimized in order to minimize chip size and maximize transistor density. Therefore, maximizing the cleanliness (and thus the area) of the substrate surface available for formation of self-aligned contacts is particularly critical to maximizing performance of devices containing such contacts. High contact resistance, in turn, adversely affects the performance of the semiconductor device. The surface of a semiconductor substrate, therefore, must be cleaned in order to manufacture a highly reliable, high performance semiconductor device.
Sputtering is a process that may result in the physical removal of surface material. Conventional technology relies on a sputtering step to clean the contact openings after the contact holes are etched. In a typical sputter etch, chemically inert ions such as argon (Ar
+
) or xenon (Xe
+
) are accelerated toward the wafer or substrate and physically eject the contaminants and impurities from the surface at the bottom of the contact openings.
Conventional sputter etching processes for cleaning contact openings have several disadvantages. First, sputtering is generally non-selective, and high-energy sputtering may seriously degrade the silicon exposed at the bottom of the etched contact opening. Moreover, sputter etching is not always effective in cleaning the contact openings, and the contact surface of the opening may be compromised because of insufficient cleaning of the bottom of the opening. In addition, the increasingly small sizes and high aspect ratios of the contact openings make it difficult for the Ar
+
or Xe
+
ions to get into the opening and even more difficult for the contaminants and impurities to be physically ejected from the bottom thereof.
In view of the aforementioned deficiencies attendant with the prior art methods, it is clear that a need exists for a method of forming contact openings that overcomes such deficiencies.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of forming contact openings.
Another object of the invention is to reduce the contact resistance in contact openings in semiconductor devices.
Yet another object of the present invention is to improve the cleanliness of the surface to be contacted.
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Bamnolker Hanna
Geha Sam
Phatak Prashant
Raghuram Usha
Cypress Semiconductor Corporation
Jr. Carl Whitehead
Kelber Steven B.
Pham Thanhha S
Piper Rudnick LLP
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