Method of forming contact holes of semiconductor device

Details Method of forming contact holes of semiconductor device Method of forming contact holes of semiconductor device

2000-12-19

2002-01-01

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S303000

Reexamination Certificate

active

06335279

ABSTRACT:

The present application claims priority under 35 U.S.C. §119 to Korean Application No. 2000-4086 filed on Jan. 27, 2000, and which is hereby incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming contact holes of a semiconductor device, in particular, forming contact holes of a semiconductor device so that damage at a field oxide layer can be prevented and processing yield can be increased as a result.
2. Description of the Related Art
In order to reduce a layout area at a portion of a chip occupying a large-area, such as a CMOS memory cell, pattern sizes and intervals between patterns should be reduced in line with the increase of the integration degree. In particular, distance between gate electrodes should also be reduced so that contacts can be formed by utilizing a self aligned contact method by which a contact overlaps the gate electrode over the gate electrode region, to reduce the total layout area. In order to apply the self aligned contact method, an insulation layer that has an etching-resistance while being etched to form a contact hole, is formed on the gate electrode. The insulation layer prevents a short with the gate electrode formed from polysilicon material. Spacers also should be provided on both sides of the gate electrode. Furthermore, spacers are formed to isolate a heavily doped region from a conductive layer of the gate electrode when an LDD type MOS transistor is formed.
In general, the thickness of the spacer for forming the LDD type transistor depends on the characteristics of the transistor. As the integration degree of a semiconductor device is increased, the distance between the gate electrodes is decreased to twice the thickness of the spacer. Insulating spacers provided on both side walls of the gate electrode should remain after implementing an etching process for forming a contact hole by applying a self aligned contact method. Therefore, a contact region with an active region of a semiconductor substrate depends on the thickness of the spacer, regardless of the pattern shapes of the gate electrodes.
Accordingly, if the spacers are formed too thickly, the exposed portion of the active region becomes too narrow. In addition, when a dry etching process is implemented on this narrow active region, the etching can stop to form an incompletely etched hole, or it can stop to form a wiring layer having high resistivity, thereby inducing a defect. Furthermore, it is difficult to fill this narrow contact hole with a wiring layer having low resistivity.
U.S. Pat. No. 5,763,312 by Jeng et al. discloses a method of fabricating a semiconductor device having LDD spacers using double spacers.
FIGS. 1A-1F
are crosssectional views explaining a method of forming the LDD spacers illustrated in U.S. Pat. No. 5,763,312.
Referring to
FIG. 1A
, a gate electrode
10
including a gate oxide layer
4
, a conductive pattern
6
and a first insulating pattern
8
is formed on an active region of a semiconductor substrate
1
which is separated into an active region and a field region by a field oxide layer
2
.
Referring to
FIG. 1B
, a first impurity doped region
12
is formed on the semiconductor substrate
1
by doping impurities having a low concentration using the gate electrode
10
as a mask.
Referring to
FIG. 1C
, a second insulating layer (not shown) is formed by blanket depositing an insulating material, preferably silicon nitride, on the semiconductor substrate to a thickness of about 400-800 Å through a chemical vapor deposition method. Then, the second insulating layer is etched back to form first spacers
14
on the side walls of gate electrode
10
. The thickness of first spacers
14
is about 300-700 Å.
Referring to
FIG. 1D
, a third insulating layer (not shown) is formed by blanket depositing an insulating material, preferably silicon oxide, to a thickness of about 400-1000 Å through a chemical vapor deposition method on the semiconductor substrate on which the gate electrode
10
and first spacers
14
are formed. Then, the third insulating layer is etched back to form second spacers
16
on first spacers
14
. The thickness of second spacers
16
is about 200-800 Å.
Referring to
FIG. 1E
, a second impurity doped region
18
is formed within the first impurity doped region
12
after forming second spacers
16
by doping impurities of high concentration into the semiconductor substrate
1
using gate electrode
10
, first spacers
14
and second spacers
16
as masks.
Referring to
FIG. 1F
, a fourth insulating layer (not shown) is formed on the semiconductor substrate
1
. The fourth insulating layer is formed by blanket depositing BPSG (Boro-Phosphosilicate Glass) or PSG (Phosphosilicate Glass) to a thickness of about 3,000-10,000 Å through a low pressure chemical vapor deposition method or a PECVD (Plasma Enhanced Chemical Vapor Deposition Method).
Next, a mask pattern (not shown) is formed on the fourth insulating layer to form contact holes. Then, the fourth insulating layer is etched by using the mask pattern as an etching mask to form contact holes in order to expose the surface of the semiconductor substrate
1
including first and second impurity doped regions
12
and
18
.
However, according to the method of forming the LDD spacers of the semiconductor device, the third insulating layer and the field oxide layer are formed from the same or similar materials. As a result, the etching ratios of the third insulating layer and the field oxide layer are identical or similar. Accordingly, a problem occurs in that a portion of the field oxide layer may be etched during implementation of the etch back process on the third insulating layer to form the second spacers. When this portion of the field oxide layer is etched, the ability of the field oxide layer to isolate each cell is reduced, thus leading to erroneous operation of the manufactured device.
Recently, the width of a contact hole has been reduced as an integration degree of semiconductor device has increased. However, the reduction of the width of the contact hole is limited. To solve this problem, a method of forming a non-overlapping contact or a borderless contact has been developed. Through this method, a distance between the contact hole and the gate electrode is kept constant while the size of the contact hole is not reduced. The contact hole is formed to overlie both active and field oxide regions.
Initially, a borderless contact method is applied by etching an interlayer dielectric formed on a semiconductor substrate to expose a portion of a field oxide layer and an adjacent surface portion of the semiconductor substrate. However at this time, a problem of forming a recess on the exposed field oxide layer is generated. That is, the depth of the recess is deeper than a source/drain junction of an active region, or is near a junction boundary, and thus a path of direct contact between a contact that is formed afterward and the semiconductor substrate results. This will induce a current leakage.
In addition, even if the contact hole is shallower than the source/drain junction of the active region, Ti and TiN which are applied to form a barrier layer during a process of forming a contact that is implemented afterward, react with silicon at the source/drain region during a heat treatment, if the contact hole is formed near the junction. When Ti and TiN react with silicon, a conductive silicide layer is formed to generate a current leakage.
In order to solve the above-described problem, a method of forming an etch stopping layer to stop an etching process for formation of a contact hole and to prevent a recess of a field oxide layer from being formed, is disclosed in U.S. Pat. No. 5,652,176 by Maniar et al.
FIGS. 2A
to
2
D are cross-sectional views explaining the conventional method of forming a borderless contact.
Referring to
FIG. 2A
, a mask pattern is formed on a semiconductor substrate
30
and a trench is formed by etching semiconduc

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