Method of forming contact

Details Method of forming contact Method of forming contact

2003-01-27

2004-11-23

Neims, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06821846

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwanese application serial no. 9113726, filed on Jun. 24, 2002.
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of forming a memory device. More specifically, the present invention relates to a method of forming a contact of a device.
2. Description of the Related Art
A dynamic random access memory (DRAM) can work with only one transistor and one capacitor. It has many advantages such as high integration, lowered production cost, superior reading/programming performance, and considerable capacitance of memory, and therefore has been widely used.
Further, as the integration of the integrated circuit increases, the area of a semiconductor device decreases. An embedded DRAM has been developed accordingly to integrate a memory cell array and a logic circuit array into a chip. The above memory has high access speed, which can be applied in a high-loading data processing system such as an image processing system. A logic circuit is operated by using a MOS transistor as a switch. An “ON” or “OFF” status is determined by a gate of the MOD transistor. For example, “ON” status of the MOS transistor is referred to as 1, and “OFF” status of the MOS transistor is referred to as 0.
In a conventional stacked DRAM, a cylindrical capacitor gets higher as the stacked DRAM needs more capacitance for storing charges. For a control circuit in the logic circuit region, a contact connects a topmost metal layer (I/O control) to a metal layer that is formed simultaneously with a bit line. The contact has a height that is equal to the sum of the dielectric layer above the capacitor, the capacitor, and the dielectric layer between the capacitor and the bit line. The contact is deeper as the capacitor is higher. Therefore, the contact has a considerable aspect ratio, which makes etching of a contact opening and filling a conductive material into the contact opening more difficult.
SUMMARY OF INVENTION
It is one object of the invention to provide a method of forming a contact, which reduces an aspect ratio of the contact formed in a logic circuit region.
It is another object of the invention to provide a method of forming a contact, which requires less time to etch a contact opening.
In one aspect of the invention, the method of the invention provides a substrate having an active device thereon. A first dielectric layer is formed over the substrate. A first metal layer is formed on the first dielectric layer. A second dielectric layer is formed on the first metal layer and the first dielectric layer. A bottom contact is formed in the second metal layer to electrically connect the first metal layer, and a node contact is formed in the first and second dielectric layers to electrically connect the active device of the substrate. A first capacitor is formed on the second dielectric layer to electrically connect to the node contact, and a middle contact is formed on the second dielectric layer to electrically connect to the bottom contact. A third dielectric layer is formed on the first capacitor, the middle contact and the second dielectric layer. A top contact is formed in the third dielectric layer to electrically connect to the middle contact. The middle contact can be formed simultaneously with the first capacitor. The bottom contact, the middle contact and the top contact constitute an objective contact of the invention, which is significantly different from a conventional high-aspect-ratio contact.
Because the objective contact of the invention consists of the top contact, the middle contact, and the bottom contact, each of which has lower aspect ratio, the prior problems with respect to high aspect can be avoided.
Furthermore, there is no problem with respect to high aspect when etching a contact opening to form the contact in the logic circuit region. The etching time can be reduced.
The top contact is compatible with the original design rule of the contact. The middle contact is formed together with the capacitor. Only one mask is required for forming the bottom contact. Therefore, the method of the present invention can be compatible with the prior process, without complicating the whole manufacture process.


REFERENCES:
patent: 6406968 (2002-06-01), Chien et al.
patent: 6537874 (2003-03-01), Nakamura et al.
patent: 6545306 (2003-04-01), Kim et al.
patent: 6562679 (2003-05-01), Lee et al.
patent: 2002/0022317 (2002-02-01), Fukuzumi

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