Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-27
2003-09-02
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S489000, C438S558000, C438S223000, C438S224000, C438S227000, C438S199000, C257S369000
Reexamination Certificate
active
06613626
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to CMOS semiconductor devices and fabrication methods therefor, and specifically to a CMOS transistor having a deep sub-micron mid-gap metal gate, which is provided to adjust threshold voltage.
The device and method of manufacture disclosed herein resolves the threshold voltage adjustment problem. The conventional process for adjusting the threshold voltage is by low energy ion implantation into an n-well. The n-well is normally doped to the order of 1·10
17
cm
−3
to 5·10
18
cm
−3
for the state-of-the-art CMOS devices. As depicted in
FIG. 1
, the initial doping density is shown by line
5
. The low energy implanted dopant distribution, to the first order, may be assumed as Gaussian distribution. Therefore the net doping near the surface is:
N
(
x
)
=
N
D
-
N
AM
exp
(
-
x
-
x
0
Δ
x
)
2
(
1
)
Where N
D
is the donor density of the n-well, N
AM
is the maximum density of the implanted acceptors, x
0
is the projected implant depth and the &Dgr;x is the Gaussian distribution constant. Both N
AM
and N
D
are large numbers. This makes control of the doping density very difficult. The doping density at the transition region from well to surface layer is the Gaussian tail. As depicted in
FIG. 1
, implant dopant density, shown by line
8
, decreases sharply in the well area
12
when implanted through the thin surface oxide layer
14
.
It is very difficult to control the threshold voltage using this prior art method on the smaller geometries required by current design constraints. For example, if the desired dopant density at the surface is 1·10
16
cm
−3
and the initial dopant density is 1·10
18
cm
−3
, the implant dopant density will need to be on the order of 1·10
18
cm
−3
plus 1·10
16
cm
−3
. This amounts to being able to know the initial dopant density to within 1% and also to control the implant dopant density to with 1% as well. This is extremely difficult. Even if the dopant density is to be reduced to a level 10% below the initial dopant density, the process tolerances will make it difficult to achieve with any precision.
The prior art process has been used for pMOST threshold voltage adjustment in n
+
polysilicon gate CMOS technology. The channel doping of an n
+
polysilicon gate nMOST is of the p-type. The channel doping of an n
+
polysilicon gate pMOST is of the n-type, having a shallow p-type surface layer. In the case of sub-micron CMOS devices, the surface p-type layer is too shallow to function properly. One solution to this problem is to change the gate electrode of pMOST devices to p
+
polysilicon. This eliminates the surface p-type layer. Although the threshold voltage is resolved, the gate depletion and high gate electrode resistance remain. Boron may diffuse through the gate oxide, causing variations in threshold voltage. These problems may be eliminated by replacing the polysilicon region at the gate with metal. The result is a metal gate CMOS structure.
The work function of mid-gap metal gate is about 0.5V lower than that of an n
+
polysilicon gate. Therefore, the channel doping density of metal gate transistors is very small compared to that of an n+or p+polysilicon gate device. The channel doping for a threshold voltage of 0.4 V is less than 1.0×10
17
/cm
3
. If this doping density is used to fabricate sub-micron devices, the channel will punch through at a very small drain voltage. Therefore, nMOST and pMOST devices require a very shallow surface p-layer and n-layer, respectively. However, when meeting the criteria to form a layer of appropriate thickness, the depth of these surface layers is so shallow, e.g., 10 nm to 30 nm, that conventional manufacturing processes lack adequate control to form a uniform layer having a desired threshold voltage.
SUMMARY OF THE INVENTION
A CMOS transistor structure is formed on a silicon substrate doped to form a active regions. Active regions are formed on the substrate by doping to a predetermined conductivity type, for example n-type or p-type. A thin layer of epitaxial silicon is overlies each of the active regions such that out-diffusion from the underlying active region dopes the epitaxial silicon. In a preferred embodiment, the thin layer of epitaxial silicon comprises additional dopants. Preferably, the additional dopants may be of the opposite conductivity type of the underlying active region, also referred to as counter dopants. Alternatively, the additional dopants may be of the same conductivity type as the underlying active region.
A method of forming a CMOS transistor on a silicon substrate comprises forming active regions by doping with a predetermined conductivity type, for example n-type or p-type, to a desired doping level; and growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage. The presence of the epitaxial layer serves to lower the threshold voltage of the underlying active region. In a preferred embodiment additional dopants are implanted into the epitaxial layer to further control the threshold voltage, by changing the doping concentration within the epitaxial layer. Preferably, ions of the opposite conductivity type as compared to the underlying active region, are implanted by ultra-shallow ion implantation. Implanting ions of the opposite conductivity type is also referred to as counter doping. This further reduces the threshold voltage. In another embodiment ions of the same conductivity type as the underlying active region are implanted by ultra-shallow ion implantation. This increases the threshold voltage to a level above associated with the out-diffused epitaxial layer, but typically below the level associate with the underlying active region.
A method of forming a CMOS transistor on a silicon substrate, comprising the steps of: depositing a silicon dioxide layer and a silicon nitride layer overlying a silicon substrate; isolating active regions by shallow trench isolation; etching away the silicon nitride layer to expose the underlying silicon dioxide layer; forming an n-well and a p-well within separate active regions by implanting ions; removing the silicon dioxide layer; growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage; forming a gate structure, source regions and drain regions; and completing the transistor.
An advantage of the invention is to provide a cost effective method for manufacturing a mid-gap metal gate CMOS integrated circuit.
Another advantage of the invention is to provide a mid-gap metal gate CMOS integrated circuit which has a high current density.
A further advantage of the invention is to provide a simple method for controlling the threshold voltage in a mid-gap metal gate CMOS.
Another advantage of the invention is to use an undoped epi-silicon layer to control the threshold voltage in a mid-gap metal gate CMOS.
A further advantage of the invention is to provide addition threshold voltage control in the mid-gap metal gate CMOS by doping the undoped epi-silicon layer
These and other advantages of the invention will become more fully apparent as the description which follows is read in conjunction with the drawings.
REFERENCES:
patent: 4777147 (1988-10-01), Scott et al.
patent: 4966861 (1990-10-01), Mieno et al.
patent: 5306667 (1994-04-01), Shappir
patent: 5338697 (1994-08-01), Aoki et al.
patent: 5665616 (1997-09-01), Kimura et al.
patent: 5668025 (1997-09-01), Blanchard
patent: 5950082 (1999-09-01), Gardner
patent: 6190179 (2001-02-01), Sundaresan
Gebremariam Samuel A
Krieger Scott C.
Loke Steven
Rabdou Matthew D.
Ripma David C.
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