Method of forming capacitor of semiconductor device

Details Method of forming capacitor of semiconductor device Method of forming capacitor of semiconductor device

1999-07-28

2001-03-27

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S256000, C438S397000

Reexamination Certificate

active

06207496

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device and, more particularly, to a method of forming a capacitor of semiconductor devices which is designed to increase the capacitor capacity by maximizing the area of the lower electrode of the capacitor.
2. Discussion of Related Art
With a development of semiconductor devices, many studies have been made to integrate more devices on a single semiconductor chip.
Especially, a variety of cell structures have been suggested in order to minimize the size of device in the dynamic random access memory (DRAM) cell.
It is desirable to construct the memory cell with one transistor and one capacitor in an aspect that the area of the device on a chip should be minimized for the sake of a very large integration.
In such a memory cell having one capacitor, signal charges are stored in the lower electrode (storage node) of a capacitor connected to the transistor (switching transistor).
With a decrease in the size of the memory cell owing to large integration of the semiconductor memory device, the capacitor becomes smaller and accordingly the number of the signal charges storable in the lower electrode decreases.
It is thus necessary that the lower electrode of the capacitor of the memory cell should be greater than a predetermined value in order to secure a capacitor capacity required to transfer desired signals without a malfunction.
To minimize the size of the memory cell, the lower electrode of capacitor must be large in area relatively within a limited region on a semiconductor substrate.
Various methods have been proposed as to enhance the surface area of the lower electrode of the capacitor.
Hereinafter, a method of forming a capacitor of semiconductor devices according to prior art will be described with reference to the accompanying drawings.
FIGS. 1
a
-
1
h
are cross-sectional views for illustrating the method of forming a capacitor of semiconductor devices according to the prior art.
As shown in
FIG. 1
a
, a first oxide layer
12
is formed on a semiconductor substrate
11
and a nitride layer
13
being formed on the first oxide layer
12
.
A photoresist (not shown) is then deposited on the nitride layer
13
. A photo-etching process is performed to selectively remove the nitride layer
13
and the first oxide layer
12
so as to expose a defined portion of the surface of the semiconductor substrate
11
, forming a plurality of contact holes
14
.
As shown in
FIG. 1
b
, polysilicon is deposited on the entire surface of the semiconductor substrate
11
including the contact holes
14
. The entire surface of the resulting material is subjected to etch back process or chemical mechanical polishing (CMP) process, forming a plug
15
inside each of the contact hole
14
.
As shown in
FIG. 1
c
, a second oxide layer
16
is formed on the entire surface of the semiconductor substrate
11
including the plugs
15
.
After the subsequent deposition of photoresist
17
on the second oxide layer
16
, the photoresist
17
is patterned by exposure and development.
As shown in
FIG. 1
d
, the patterned photoresist
17
is used as a mask in selectively removing the second oxide layer
16
to expose the surface of the nitride layer
13
adjacent to the plugs
15
.
The nitride layer
13
is used as an etching stopper layer in selectively removing the second oxide layer
16
.
As shown in
FIG. 1
e
, the photoresist
17
is removed and the second oxide layer
16
selectively removed is wet-etched to broaden a region in which the lower electrode of capacitor will be formed.
That means, the capacitor capacity of the lower electrode that will be formed later is enhanced because the distance between the lower electrodes of the capacitor decreases by selectively removing the second oxide layer
16
by the wet etching process.
In performing the wet etching, the second oxide layer
16
is etched further in the upper part than the lower part because of the loading effect.
Unexplained part “A” is a portion of the second oxide layer
16
removed by the wet etching.
As shown in
FIG. 1
f
, a conductive layer
18
for the lower electrode of the capacitor electrically connected to each of the plug
15
is formed on the entire surface of the semiconductor substrate
11
including the remaining second oxide layer
16
. A third oxide layer
19
is then formed on the conductive layer
18
.
As shown in
FIG. 1
g
, an etch back process or CMP process is performed on the entire surface of the second oxide layer
19
and the conductive layer
18
so as to expose the surface of the second oxide layer
16
, selectively removing the third oxide layer
19
and the conductive layer
19
and forming a lower electrode
18
a
of capacitor having an inner-type crown structure.
As shown in
FIG. 1
h
, a wet etching is performed to remove the third oxide layer
19
and the second oxide layer
16
. On the lower electrode
18
a
of capacitor are sequentially formed dielectric layer
20
and upper electrode
21
of capacitor, finally completing the related art process for forming a capacitor.
In the related art method of forming a capacitor of semiconductor devices, however, there are several problems as folLows.
First, an additional wet etching process is required in reducing the distance between the lower electrodes in the photo-etching process when fabricating an inner-type capacitor. Thus the process becomes complicated.
That means, it is necessary to carry out another wet etching process because the minimum distance between the lower electrodes in the 256M DRAM is less than 0.1 &mgr;m and thus defining a desired distance between the lower electrodes in the photo-etching process is difficult to realize.
Second, uniform wet etching of the entire cells is not easy to realize because the area to be wet-etched is increased with an inclination that the capacitor increases in height, and the aspect ratio becomes larger.
Third, the upper part of the lateral sides of each cell is further wet-etched due to the loading effect in such a manner that it is impossible to reduce the distance between the lower electrodes sufficiently.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method of forming a capacitor of semiconductor devices which is to enhance the capacitor capacity by minimizing the distance between the lower electrodes and maximizing the area of the lower electrode in the process of fabricating a capacitor having an inner-type crown structure.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method of forming a capacitor of semiconductor devices includes the steps of: forming a first insulating layer having a plurality of contact holes on a semiconductor substrate; forming a plug in each of the contact holes; sequentially forming a second insulating layer and a mask layer on the entire surface of the semiconductor substrate; selectively removing the mask layer to form a plurality of first mask patterns having a first line width between the plugs; selectively removing the first mask pattern to form second mask patterns having a second line width smaller than the first line width; removing the second insulating layer by using the second mask patterns as a mask so as to expose the plugs; sequentially forming a conductive layer and a third insulating;layer on the entire surface of the semiconductor substrate for the sake of electrical connection to each plug; removing materials overlying the second insulating layer to expose the surface of the second insulating layer, and fo

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