Method of forming buried straps in DRAMs

Details Method of forming buried straps in DRAMs Method of forming buried straps in DRAMs

1999-11-23

2001-10-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S244000, C438S247000, C438S423000

Reexamination Certificate

active

06297089

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits and more particularly to an improved method of forming the buried strap that connects the source of the array transfer transistor to an electrode of the storage capacitor in each memory cell of DRAM chips.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor integrated circuits and particularly in Dynamic Random Access Memory (DRAM) chips, connecting straps are extensively used. As is known to those skilled in the art, in DRAM chips, an array transfer transistor, typically an Insulated Gate Field Effect Transistor (IGFET) and a storage capacitor are associated to form the elementary memory cell. The strap connects the source region of the IGFET transistor and an electrode of the storage capacitor to allow an electrical contact therebetween. In the last generation of DRAM chips, due to scaling reduction effects, the storage capacitor is formed in a trench etched in the silicon substrate. In this case, the strap which consists in the combination of a doped region formed by ion implantation in the silicon substrate and a doped polysilicon stud is usually referred to in the technical literature as the “buried strap”.
The buried strap is fabricated early in the wafer fabrication process flow. It must ensure an excellent electrical connection at only a small processing cost while requiring little silicon area. However, it must not degrade the retention time of the memory cell.
A conventional buried strap (BS) formation process is described hereinbelow in conjunction with FIG.
1
and
FIGS. 2A
to
2
F. All the processing steps are conducted in the so-called Deep Trench Module.
FIG. 1
schematically illustrates the starting structure referenced
10
which basically consists of a P-type doped silicon substrate
11
with a 10 nm thick silicon oxide (SiO
2
) and a 170 nm thick silicon nitride (Si
3
N
4
) layer, respectively referenced
12
and
13
formed thereon. These two layers will be referred to hereafter as the Si
3
N
4
pad layer
13
for brevity. Silicon substrate
11
includes an N type doped layer and a P type doped layer labeled N-band and P-well respectively as standard. Deep trenches
14
have been conventionally etched in the silicon substrate
11
. A dual nitride-oxide (NO) dielectric film
15
coats the bottom surface of the trench
14
. As is apparent in
FIG. 1
, a doped polysilicon fill (POLY1) referenced
16
has been recessed to a depth of about 1.2 &mgr;m. An 8 nm thick thermal silicon oxide layer
17
passivates the vertical walls of the trench above the POLY1 material and the bottom of the trench above the polysilicon fill
16
. The N-band and the N type heavily doped “buried plate” (shown in dotted line in
FIG. 1
) on the one hand and the doped polysilicon fill
16
(POLY1) on the other hand form the two electrodes of the storage capacitor that are isolated one from another by the dielectric film
15
. Typically, the trench
14
has a depth of about 7 &mgr;m and an oblong section of about 500*350 nm at the substrate
11
surface. Finally, a TEOS SiO
2
collar layer
18
having a thickness of about 60 nm is conformally deposited by LPCVD to coat structure
10
top surface. For instance, the TEOS Sio
2
material can be deposited in a TEL ALPHA 8S tool using the process parameters recited below.
TABLE 1
Pressure
1
Torr
Temperature
675°
C.
TEOS flow
200
cc/min
N
2
flow
100
cc/min
Duration
17
min
The target is to obtain a thickness of about 60 nm atop the structure
10
surface (measured on a monitor wafer) and a thickness of about 30 nm on the sidewall. After TEOS SiO
2
deposition, an anneal is performed in a SVG VTR 7000+ tool for TEOS SiO
2
material densification. Anneal conditions are:
TABLE 2
Duration
20
min
Temperature
1000°
C.
N
2
flow
20
l/min
Now, the TEOS SiO
2
collar layer
18
is first anisotropically etched down to the Si
3
N
4
pad layer
13
. This dry etch step is controlled by an optical etch end-point technique (CN line) using an optical emission spectrometer. When the surface of the pad Si
3
N
4
layer
13
is reached, the etching is stopped. Because of topology differences between the array and kerf/support areas at the wafer surface, the TEOS SiO
2
material is etched more in the trenches. It is essential that the collar layer
18
remains at the top of the trench
14
as illustrated in
FIG. 2A
at about half the Si
3
N
4
pad layer
13
thickness. On the other hand, no TEOS SiO
2
of the collar layer
18
must remain at the bottom of the trench
14
, so that the doped polysilicon fill
16
surface is exposed to subsequently ensure an excellent electrical contact between the drain region of the IGFET and the polysilicon fill
16
forming a first electrode of the storage capacitor. Preferably, this step is continued by a cleaning step still performed in the same reactor to ensure polymer residue removal from the reactor walls.
For instance, when the above dry etching step is performed in the M×P+ chamber of an AME 5200 tool, commercially available from Applied Materials, Santa Clara, Calif., USA, operating conditions recited below are adequate.
TABLE 3
Dry Etch
Pressure
75
mTorr
Power
500
w
Temperature
20-40°
C.
Backside cool.
2
Torr
Magnetic field
40
G
C
4
F
8
/Ar flow
8/125
sccm
Duration
30
s
A TEOS SiO
2
etch rate 6 times faster than Si
3
N
4
is ensured with this C
4
F
8
/Ar selective chemistry. This step will be referred to hereinbelow as the collar etch-back step.
Then, the native oxide is stripped with a conventional wet process. For instance the wafer is cleaned first using a BHF solution, then a DHF Huang A/B solution to reduce contact resistance. A 330 nm thick composite layer of amorphous/arsenic doped/amorphous polysilicon material is conformally deposited onto the structure
10
by successive depositions using silane/arsine/silane gas in a LPCVD reactor such as a SVG VTR 7000+ which includes two pairs of injectors installed one at the top and the other at the bottom of the reactor. Operating conditions are briefly summarized in Table 4 below.
TABLE 4
Gas
silane
arsine
silane
Top Flow
130 sccm
100 sccm
130 sccm
Bottom Flow
30 sccm
30 sccm
Temp.
550° C.
550° C.
550° C.
Pressure
600 mTorr
120 mTorr
600 mTorr
Duration
12 min
10 min
146 min
The composite layer referenced
19
in
FIG. 2B
(also referred to as POLY2) fills the trenches of all the memory cells. As is known to those skilled in the art, arsenic is an N type dopant.
The POLY 2 material of layer
19
is first planarized by chemical-mechanical polishing in a WESTECH 372 M polisher with a conventional slurry. This step is followed by a brush cleaning to reduce contamination. Next, it is partially removed from the trench
14
in a DPS chamber of an AME 5200 tool, for instance in a SF
6
atmosphere. As a result, there is produced the recess illustrated in FIG.
2
C. This latter step leaves a doped polysilicon (POLY2) stud still referenced
19
in the trench
14
. The bottom of the recess is about at 120 nm under the silicon substrate
11
surface. Recess depth is controlled by laser etch end-point monitoring.
Now, the exposed TEOS SiO
2
material of collar layer
18
and the thermal SiO
2
material of layer
17
are removed from the upper part of the trench
14
to expose a portion of the trench top side wall by means of a conventional wet process which is known to be isotropic. As is apparent in
FIG. 2D
, this step etches these materials in some extent under the POLY2 stud
19
surface. Typical operating conditions when a DAI-NIPPON SCREEN (DNS) wet bench tool is used are:
TABLE 5
Step 1: BE
: NH
4
F:HF:H2O
 5:1:48
at 22° C.
(in volume)
during 145 s
Step 2: Huang A
: H
2
O:H
2
O2:NH
4
OH
10:1:1
at 22° C.
during 5 min
Step 3: Huang B
: H
2
O:HCl:H
2
O2
10:1:1
at 30° C.
during 5 min
This wet etch step will be referred to hereinbelow as the collar recess step.
The first element of the buried strap is now formed by ion implantation of phosphorus atoms in the substrate
11
to create N type heavily doped regions

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