Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-02-28
2008-12-09
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S638000, C438S673000, C438S620000, C438S508000
Reexamination Certificate
active
07462536
ABSTRACT:
A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.
REFERENCES:
patent: 5502008 (1996-03-01), Hayakawa et al.
patent: 6875684 (2005-04-01), Jin et al.
Cho Whee Won
Hong Seung Hee
Jeong Cheol Mo
Kim Jung Geun
Hynix / Semiconductor Inc.
Le Dung A.
Townsend and Townsend / and Crew LLP
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