Method of forming barrier layers for damascene interconnects

Details Method of forming barrier layers for damascene interconnects Method of forming barrier layers for damascene interconnects

2000-08-18

2002-03-19

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S633000, C438S687000

Reexamination Certificate

active

06358832

ABSTRACT:

TECHNICAL FIELD
The present invention relates to formation of multi-level interconnects in a semiconductor by the damascene process. In particular, this invention relates to the formation of diffusion barrier layers, reactive ion etch (RIE) stop layers, and chemical-mechanical polishing (CMP) stop layers for damascene interconnects.
BACKGROUND OF THE INVENTION
Metallization patterns on integrated circuits can be formed by depositing a dielectric layer, patterning the dielectric layer by photolithography and reactive ion etching (RIE) to form a groove or trench, and depositing a metal layer that fills the trench in the dielectric layer. The metal layer typically not only fills the trenches but also covers the entire semiconductor wafer. Therefore, the excess metal is removed using either chemical-mechanical polishing (CMP) or an etchback process so that only the metal in the trenches remains.
This process, called the “damascene process,” forms conductors in-laid in the dielectric layer. The process avoids the problems associated with metal etching, such as lack of suitable dry-etch plasma chemistries, problems in dimension control, the formation of small gaps that are difficult to fill with the subsequent dielectric layer, and the entrapment of impurities in inter-wiring spaces. This process is described in U.S. Pat. No. 4,944,836 issued to Beyer.
The term “damascene” is derived from the name of a centuries-old process used to fabricate a type of in-laid metal jewelry first seen in the city of Damascus. In the context of integrated circuits, damascene means formation of a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Planarity is essential to the formation of fine-pitch interconnect levels because lithographic definition of fine features is achieved using high-resolution steppers having small depths of focus. The “dual damascene” process, in which conductive lines and stud via metal contacts are formed simultaneously, is described in U.S. Pat. No. 4,789,648 issued to Chow.
As wire widths in integrated circuits continue to shrink, the electrical conductivity of the wiring material becomes increasingly more important. The material of choice since the integrated circuit art began, aluminum, is becoming less attractive than other materials, such as gold, copper, and silver, which are better conductors. In addition to possessing superior electrical conductivity, these materials are more resistant than aluminum to electromigration, a property that increases in importance as wire cross-sectional areas decrease and applied current densities increase. In particular, copper is seen as an attractive replacement for aluminum because copper offers low cost, ease of processing, lower susceptibility to electromigration, and lower resistivity.
Copper has not as yet been widely used for wiring because it has several serious disadvantages. It can diffuse rapidly into and through silicon substrates and dielectric films, such as silicon dioxide. Diffusion into an adjacent dielectric region can cause formation of a conductive path between two interconnect lines producing an electrical short. Diffusion into an adjacent silicon substrate can cause junction leakage, thereby destroying the device. Copper is easily oxidized during subsequent processing steps, but, unlike aluminum, does not have a hard, stable, self-limited native oxide. Copper also has poor adhesion to capping dielectric layers. Replacement of aluminum with copper as an interconnect material requires that these problems be overcome.
J. E. Cronin et al., “Copper/Polyimide Structure with Selective Cu
3
Si/SiO
2
Etch Stop,” IBM Tech. Discl. Bull., 37(6A), 53-54 (June, 1994), and U.S. Pat. No. 5,447,887 issued to Filipiak, each disclose formation of an intermediate copper silicide layer between a copper layer and a silicon nitride layer to improve adhesion of the copper to the silicon nitride layer. Although the copper silicide layer improves adhesion between the copper and the silicon nitride layer, however, it does not act as a diffusion barrier. Furthermore, copper silicide is thermally unstable at temperatures above about 300-350° C. and may dissociate with concomitant adhesion loss at this interface. In addition, formation of the layer consumes a portion of the underlying copper layer, and silicon dissolved in the copper increases the interconnect resistivity.
The various metal caps that have been proposed are not suitable for ultra large scale integration or ultra large scale integrated circuit (ULSI) applications because they do not have the RIE etch-stop behavior needed for etching vias from above. When finite alignment registration error is present between adjacent lithographic levels, lack of a suitable RIE etch-stop can produce via overetch, which can cause via-to-underlying via or via-to-underlying interconnect shorts. Alignment registration error is a statistical possibility in the production of multi-level interconnects and must be tolerated in a multi-level interconnect technology.
To overcome the shortcomings of existing damascene interconnects, a new interconnect is provided. An object of the present invention is to provide an improved interconnect in which the conductive material, typically copper, does not diffuse into the surrounding regions. A related object is to provide an interconnect in which conductive material is not exposed to an oxidizing atmosphere. Another object is to provide an interconnect in which the conductive material adheres to the overlying material. Still another object is to provide an interconnect that has a blanket reactive ion etch-stop.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides, in one embodiment, a structure in which the conductive material, preferably copper, is capped with a conductive reactive ion etch-stop and diffusion barrier, and the inter-metal spacings are capped with an insulating dielectric etch-stop layer that is also a chemical mechanical stop-layer. In one embodiment, the structure comprises: a substrate; a dielectric layer over the substrate; a chemical mechanical polish-stop layer over the dielectric layer; an opening in the dielectric layer and the chemical mechanical polish-stop layer; a conductive liner lining the opening; a conductive material filling the opening and in electrical contact with the conductive liner; a conductive metal diffusion barrier cap over the conductive material; and a dielectric etch-stop layer over the chemical mechanical polish stop-layer, the liner, and the metal diffusion barrier cap. The upper surface of the chemical mechanical polish-stop layer and the upper surface of the conductive material are coplanar. The conductive metal diffusion barrier cap is in contact with the conductive material.
In this structure, the conductive metal diffusion barrier cap provides adhesion improvement, corrosion protection, and electromigration resistance improvement. These advantages are achieved by bonding the conductive metal diffusion barrier cap at the surface of the conductive material, which impedes diffusion of the atoms of conductive material under electrical current stresses. The conductive material is completely encapsulated in a diffusion barrier in a manner that decouples the needs of reactive ion etch-stop, CMP-stop performance, or both from the diffusion barrier performance of the conductive metal diffusion barrier cap.
In another aspect, the invention is a method for forming the structure. The method comprises the steps of:
(A) depositing a dielectric layer on substrate;
(B) depositing a chemical mechanical polish-stop layer on the dielectric layer;
(C) forming an opening in the dielectric layer;
(D) depositing a conductive liner in the opening;
(E) depositing a conductive material in the opening:
(F) removing the excess conductive material;
(G) depositing a conductive metal diffusion barrier cap on the conductive material; and
(H) depositing a dielectric etch-stop on the conductive material and dielectric lay

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