Method of forming asymmetric source/drain for a DRAM cell

Details Method of forming asymmetric source/drain for a DRAM cell Method of forming asymmetric source/drain for a DRAM cell

2000-06-15

2001-10-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000, C438S299000, C438S303000

Reexamination Certificate

active

06297105

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming asymmetric source/drain for a DRAM cell and more particularly to a method of forming transistors with reduced short channel effect (SCE) and junction leakage current so as to improve the reliability of a DRAM device.
2. Description of the Prior Art
As the function of a microprocessor is becoming more and more powerful and the operation scale of computer programs software is becoming larger and larger, the demand for increasing the memory capacity of a memory storage device increases substantially. Strong demand for high capacity memory storage have provided a driving force pushing the semiconductor manufacturing technology to a higher level of integration, which aims at fabricating low-cost memory devices with high memory capacity. Attributed to 1T1C (1-Transistor, 1-Capacitor) structure adopted by DRAM cell higher integration level in comparison with other types of memory devices can be realized. The size of a transistor in a DRAM cell is therefore shrunk in order to increase the level of integration in a DRAM device. However, as the size is reduced to a sub-micron level, short channel effect (SCE) and junction leakage current become very serious problems.
When the problem of a junction leakage current occurs, the charges stored in the capacitor of a DRAM can leak, which then leads to an aggravated decaying of the sensing signal during each refresh cycle. Although by raising the frequency of the refresh cycle the above-mentioned problem can be resolved; however, the operation of raising the frequency of the refresh cycle by itself can seriously and adversely affect the performance of the entire system.
Conventionally, one of the methods used to solve above-mentioned problems is the method of forming symmetrically graded junctions in the substrate on opposite sides of the gate electrode to suppress the junction leakage, which subsequently improves the cell charge retention. However, this method tends to exacerbate the short channel effect. Another method forms symmetric abrupt junctions in the substrate on opposite sides of the gate electrode to suppress the short channel effect. However, this second method tends to dramatically worsen the junction leakage problem, especially the gate-induced-drain-leakage (GIDL), which subsequently exacerbate the leakage of the stored charges.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a fabrication method of forming asymmetric sources/drains for a DRAM cell to alleviate the problems of short channel effect and junction leakage current, which subsequently can improve a DRAM cell's charge retention.
Moreover, the present invention provides a method of forming asymmetric sources/drains for a DRAM cell in order to reduce the size of the DRAM cell for increasing the integration level and bit capacity of the DRAM cell without affecting the charge storage ability and refresh frequency.
To achieve the above-mentioned objects, the method of forming asymmetric source/drain for a DRAM cell according to the present invention comprises the steps of forming a graded junction on one side of a gate structure in a substrate to be used as a node contact region and forming an abrupt junction on the other side of the gate structure in the substrate to be used as a bit line contact region.
According to an embodiment of the present invention, the method for forming the graded junction involves the implantation of P
31
ions, whereas the method for forming the abrupt junction involves the implantation of P
31
ions or As
75
ions, or both. Furthermore, the method for forming the graded junction comprises the steps of forming a spacer on both sides of the gate structure after a doped region is formed on one side of the gate structure in the substrate, followed by the forming of a SAC doped region below the doped region.


REFERENCES:
patent: 4851360 (1989-07-01), Haken et al.
patent: 4935379 (1990-06-01), Toyoshima
patent: 5926707 (1999-07-01), Seo
patent: 6162669 (2000-12-01), Horita et al.

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