Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-11
2002-02-19
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S586000, C438S723000, C438S724000, C438S009000
Reexamination Certificate
active
06348389
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a method of forming and etching a resist protect oxide (RPO) layer which has improved etch selectivity to a shallow trench isolation and an increased pre-metal dip processing window.
2) Description of the Prior Art
Shallow trench isolations (STI) are widely used in semiconductors manufacturing to provide isolation of active areas on a substrate. The inventors use a resist protect oxide (RPO) in conjunction with an STI to mask a first area while selectively forming silicide on a second area. However, STI's are susceptible to a problem known as the corner recess problem. Device processing requires an RPO etch step (wet etch) after the STI has undergone chemical mechanical polishing (CMP) to its final size. To assure that the RPO layer is completely removed an overetch is used. This overetch inevitably etches away part of the exposed STI causing corners of the STI to be recessed. Recessed corners can cause junction leakage associated with salicide formation.
Another problem with the inventors' RPO process is that the subsequent pre-metal (wet etch) dip processing window is narrow. If too little etch is performed during pre-metal dip, traces of oxide or other contaminants may remain on the poly layer causing the poly layer to be unstable. Too much etch during pre-metal dip will remove too much of the RPO layer, which can cause silicide formation on the I/O area (e.g. masked second area). Because of this narrow processing window, it is extremely difficult to successfully perform rework of the pre-metal dip step.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 4,635,347 (Lien et al.) shows a self-aligned TiSi
x
gate and contact forming process.
U.S. Pat. No. 5,792,684 (Lee et al.) shows a SiN layer overlying a FOX structure.
U.S. Pat. No. 5,757,045 (Tsai et al.), U.S. Pat. No. 5,723,893 (Yu et al.), and U.S. Pat. No. 5,605,853 (Yoo) show TiSi
x
processes.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming and etching a resist protect oxide layer which provides a reduced corner recess in a shallow trench isolation.
It is another object of the present invention to provide a method for forming and etching a resist protect oxide layer which provides an increased pre-metal dip processing window.
It is yet another object of the present invention to provide a method for forming and etching a resist protect oxide layer which allows for rework of a subsequent pre-metal dip step.
To accomplish the above objectives, the present invention provides a method for forming and etching a resist protect oxide layer, which provides improved etch selectivity to a shallow trench isolation and an increased pre-metal dip processing window. The process begins by forming a shallow trench isolation on a semiconductor substrate having a first area and a second area. A gate is formed on the semiconductor substrate in the first area, adjacent to the shallow trench isolation. Impurity ions are implanted into the semiconductor substrate to form source and drain regions. In a key step, a resist protect oxide layer comprising a thin silicon oxide layer (
22
) and an overlying thin nitrogen containing layer (
24
), is deposited over the semiconductor substrate, the gate, and the shallow trench isolation. The thin nitrogen containing layer (
24
) can be composed of silicon nitride or silicon oxynitride. Alternatively, if the notrogen containing layer (
24
) is composed of silicon oxynitride, the oxide layer (
22
) can be omitted because oxynitride's stress is less than nitrogen, so the oxynitride could use a native oxide layer as the buffer oxide. The resist protect oxide layer is patterned in an RPO etch step; thereby exposing the first area, including the source and drain regions. A key advantage of the invention is that the RPO etch step can be performed in an end-point mode where the endpoint is detected by the nitrogen content of the etch chamber ambient. Silicide regions can then be formed on the source and drain regions. Semiconductor fabrication continues using conventional process to form dielectric layers, contacts and interconnections.
The present invention provides considerable improvement over the prior art. Because the RPO etch is performed in an end-point mode, the present invention provides a method for forming a gate with a reduced corner recess in an adjacent shallow trench isolation. The end-point mode RPO etch reduces the amount of overetch required to completely remove the RPO layer. The RPO layer can be completely removed from over the source and drain regions while the shallow trench isolation suffers much less corner recessing than in conventional processes. Because there is a much less recessed corner on the shallow trench isolation, trapped polysilicon and nitride residues are reduced. Also, juction leakage associated with salicide formation is reduced.
Another advantage of the present invention is that it proivdes a larger pre-metal dip processing window than a conventional process. In a conventional process a longer pre-metal dip or a rework pre-metal dip will etch the RPO layer covering the second area. This can cause silicide formation in the second area. In the present invention, the thin nitrogen containing layer is exposed to the pre-metal dip. Because the silicon nitride or silicon oxynitride of the thin nitrogen containing layer etch much slower in a HF wet etch than silicon oxide, the pre-metal dip processing window is larger in the process of the present invention. The larger processing window can allow for rework of the pre-metal dip.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 4635347 (1987-01-01), Lien et al.
patent: 5200028 (1993-04-01), Tatsumi
patent: 5286667 (1994-02-01), Lin et al.
patent: 5674356 (1997-10-01), Nagayama
patent: 5683548 (1997-11-01), Hartig et al.
patent: 5719079 (1998-02-01), Yoo et al.
patent: 5723893 (1998-03-01), Yu et al.
patent: 5757045 (1998-05-01), Tsai et al.
patent: 5792684 (1998-08-01), Lee et al.
patent: 5998252 (1999-12-01), Huang
patent: 6004829 (1999-12-01), Chang et al.
patent: 6013943 (2000-01-01), Cathey et al.
patent: 6025267 (2000-02-01), Pey et al.
Chang Tzong-Sheng
Chou Chen Cheng
Ackerman Stephen B.
Pompey Ron
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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