Method of forming analog capacitor dual damascene process

Details Method of forming analog capacitor dual damascene process Method of forming analog capacitor dual damascene process

2001-04-27

2003-07-22

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06596579

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit fabrication. More particularly, the invention relates to forming metal-insulator-metal capacitor structures in a dual damascene fabrication process.
BACKGROUND
Processes for forming a metal-insulator-metal capacitor in a copper dual damascene process in an integrated circuit, such as a complimentary metal oxide semiconductor structure, generally require etching a via through an intermetal dielectric layer to expose a copper top plate of the capacitor. Another via generally must be etched through the intermetal dielectric layer and through a capacitor dielectric layer to expose a copper bottom plate of the capacitor. In prior processes, the etching step to form the vias had to be carefully controlled to ensure that the etching of the via to the top plate did not break through the capacitor dielectric and into the bottom plate, thereby causing an electrical short between the top and bottom plates. To help prevent such etch-through, the top plate was made relatively thick, such as about 1000-1400 angstroms. However, thickening the capacitor top plate introduced difficulties in subsequent dual damascene process steps for forming conductor trenches.
What is needed, therefore, is a process for forming metal-insulator-metal capacitor structures wherein timing constraints on via etch steps may be relaxed, while at the same time minimizing the thickness of the top capacitor plate to simplify the dual damascene trench-formation processes.
SUMMARY
The above and other needs are met by a process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent to the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section.
An upper dielectric layer is formed adjacent the second capacitor electrode section. Portions of the upper dielectric layer, and possibly the second capacitor electrode section, are selectively removed to form a first via cavity that extends through the upper dielectric layer and possibly into or through the edge portion of the second capacitor electrode section. This exposes the edge portion of the second capacitor electrode section within the first via cavity. The first via cavity is filled with a via metal, which makes electrical connection with the edge portion of the second capacitor electrode section that is exposed within the first via cavity.
Because the edge portion of the top electrode layer does not overlie the bottom electrode layer, it is not necessary to stop the via etch exactly at the top surface of the top electrode layer, as is typically required. Thus, the typical constraints in regard to etch selectively when drilling the vias through the dielectric layer overlying the top electrode are no longer applicable. This allows for a more robust integration of capacitor processing with dual damascene copper processing. Further, because the top electrode layer does not need to function as an etch stop for the via drilling process, the top electrode layer can be of any material desired that is compatible with the other processing constraints and desired functions. In addition, the top electrode layer may be formed at a thickness that is much thinner than prior art top electrode layers that needed to function as an etch stop. Further, additional layers adjacent or near the top electrode layer, which function only or primarily as etch stops, are also no longer required.
In another aspect, the invention provides an integrated circuit having a capacitor formed according to the process described above.


REFERENCES:
patent: 5580814 (1996-12-01), Larson
patent: 6511874 (2003-01-01), Zambrano

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