Method of forming an ultra-thin SOI electrostatic discharge prot

Details Method of forming an ultra-thin SOI electrostatic discharge prot Method of forming an ultra-thin SOI electrostatic discharge prot

1998-05-20

2000-06-27

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438200, 438151, 438207, 438330, 438303, 438156, H01L 2714

Patent

active

060806125

ABSTRACT:
A method of forming, on an ultra-thin SOI substrate, an ESD protected device, includes: preparing a single crystal silicon substrate, including forming insulated areas thereon and forming selectively conductive areas thereon; doping the selectively conductive layers with dopants; growing, epitaxially, silicon layers over selected insulated areas and the doped, selectively conductive areas; heating the substrate and the structures formed thereon at between about 850.degree. C. to 1150.degree. C. for between about 30 minutes to three hours to redistribute the dopant into the epitaxially grown silicon layer; completing the fabrication of additional layers in the structure; and metallizing the structure.

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Article entitled, "ESD Reliability and Protection Schemes in SOI CMOS Output Buffers" by M. Chan, S. Yuen, Z-J Ma, K. Y. Hui, P. K. Ko and C. Hu published in the IEEE Transactions on Electron Devices, vol. 42, No. 10, Oct. 1995, pp. 1816-1821.
Article entitled, "EOS/ESD Protection Circuit Design for Deep Submicron SOI Technology" by S. Ramaswamy, P. Raha, E. Rosenbaum and S-M. Kang published in OES/ESD Symposium 95-212 to 95-217, pp. 4.7.1 to 4.7.6.
Article entitled, "Dynamic Threshold Body--and Gate-Coupled SOI ESD Protection Networks" by S. Voldman. F. Assaderaghi, J. Mandelman, L. Hsu and G. Shahidi, published in EOS/ESD Symposium, 97-210 to 97-220, pp. 3A.2.1 to 3A.2.10.

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