Method of forming an oxide layer

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate

Reexamination Certificate

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C438S758000, C438S769000, C438S770000, C438S774000, C438S775000

Reexamination Certificate

active

06407008

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of manufacturing semiconductor devices and, ore particularly, to a method of forming an oxide layer on silicon using an ambient comprising N
2
O.
2. Description of the Related Art
With the continuing scaling down of the feature size of semiconductor devices, the quality of ultra-thin oxides, such as gate dielectrics, has become more and more critical to the performance of the semiconductor devices. Further, advanced semiconductor devices require gate oxides less than 30 Angstroms (Å) thick. Oxides this thin are hard to control in conventional tube furnaces due to the difficulty of quickly supplying and removing oxygen from the system.
Rapid thermal processing (RTP) has been used to form quality ultra-thin oxides in MOSFET devices to avoid the problems of the conventional furnace processing. RTP technology is a natural choice for forming quality ultra-thin oxides because it can precisely control the oxide formation process. Rapid wafer heating and cooling, rapid gas switching, and high process temperature produce short oxidation cycles in RTP.
Additionally, oxides produced by RTP are known to possess a better oxide quality and a smoother Si/SiO
2
interface compared to conventional furnace processed oxides.
Another advantage of RTP is the lower thermal budget compared to conventional furnace processing. Thermal budget refers to the maximum acceptable diffusion of dopants in a semiconductor device containing doped regions. In manufacturing highly integrated semiconductor devices, the regions of dopants in the wafer must be precisely controlled. For example, dopant diffusion must be limited to maintain shallow junctions vertically and horizontally. In conventional furnace processes, dopant diffusion is difficult to control because the process is performed at high temperatures for relatively long periods of time.
Different ambient gases have also been tried. For example, pure O
2
and wet O
2
(steam mixed with O
2
) have been used as an oxidation ambient in the formation of oxide. In pure O
2
and wet O
2
based-oxides, however, the migration of dopants, particularly boron, from an overlying polysilicon layer down through the oxide to the channel, has caused the degradation of device performance by altering the doping profile of the channel region.
More recently, N
2
O has been used as an oxidation ambient because, compared to pure O
2
and wet O
2
based-oxides, N
2
O-based nitrided oxides are found to be a better barrier against boron penetration from the polysilicon gate into the channel region of MOSFET devices. Further, N
2
O-based nitrided dielectrics are known to provide relatively fine oxide reliability. Also, higher charge-to-breakdown and better hot carrier immunity can be obtained in N
2
O-based nitrided oxides.
For these reasons, RTP systems utilizing atmospheres containing N
2
O have been studied as a way to obtain high-quality oxides. For example, U.S. Pat. No. 5,882,993 utilizes rapid thermal anneal in an atmosphere of N
2
O/NH
3
/O
2
/HCl, or N
2
O/O
2
/HCl, or NO/O
2
/HCl for gate oxide formation. Also, U.S. Pat. No. 5,880,040 discloses a two-step RTP with a first oxidation step in N
2
O and a second step in NO ambient.
However, there have been drawbacks to these conventional processes. First, non-uniformity is often found in oxides grown in pure N
2
O. Second, as oxides grown in N
2
O and O
2
gas mixture become thinner, as required by deep sub-micron MOSFET devices, boron can penetrate through the oxide layer. Thus, further improvement in this respect is needed. Third, in the case of RTP requiring multiple-step processes, the processes are more complex and it is difficult to control the thickness of an oxide layer and its uniformity. Also, more steps usually mean an increase in processing cycle time and lower throughput. Fourth, when NH
3
is used in the oxidation ambient, NH
3
can introduce raps in the oxides that cause degradation in device performance.
Accordingly, there is still a need for improvement in forming ultra-thin oxides with high quality oxide characteristics such as more resistance to the penetration of dopants such as boron and increased charge-to-breakdown.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to improve the quality of an ultra-thin oxide layer and to improve the formation methods thereof.
In accordance with the present invention, a semiconductor substrate having an exposed silicon surface is placed into a thermal process chamber. Then, an ambient gas comprising N
2
O and an inert gas such as argon or N
2
is introduced into the process chamber. Next, the semiconductor surface is heated to a predefined process temperature to oxidize at least a portion of the exposed silicon surface. Finally, after a predefined process time, the semiconductor substrate is cooled.
Preferably, the heating step comprises rapid thermal oxidation.
In another embodiment of the present invention, an oxidation ambient gas further includes O
2
.
In accordance with the present invention, more nitrogen can be incorporated in the ultra-thin oxide layer, thereby allowing more boron penetration resistance. Also, better oxide characteristics, such as uniform oxide composition and thickness uniformity, and increased charge-to-breakdown in the oxide layer, can be achieved in the present invention compared to the conventionally processed thin oxides.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention that proceeds with reference to the accompanying drawings.


REFERENCES:
patent: 5244843 (1993-09-01), Chau et al.
patent: 5407870 (1995-04-01), Okada et al.
patent: 5498577 (1996-03-01), Fulford, Jr. et al.
patent: 5512519 (1996-04-01), Hwang
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5738909 (1998-04-01), Thakur et al.
patent: 5877057 (1999-03-01), Gardner et al.
patent: 5880040 (1999-03-01), Sun et al.
patent: 5882993 (1999-03-01), Gardner et al.
patent: 5970350 (1999-10-01), Gardner et al.
patent: 07193059 (1995-07-01), None

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