Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-01-21
2010-11-02
Stark, Jarrett J (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S183000, C257SE21672
Reexamination Certificate
active
07824988
ABSTRACT:
A method includes forming a source, a drain, and a disposable gate (38) of the first transistor; forming a source, a drain, and a disposable gate of the second transistor; removing the disposable gates of the first transistor and the second transistor; forming a photoresist layer over the first transistor and the second transistor; patterning the photoresist layer to expose a gate region of the first transistor and a gate region of the second transistor; and implanting the substrate under the gate region of the first transistor and under the gate region of the second transistor, wherein implanting the substrate under the gate region of the first transistor provides a permanent shorting region between the source and the drain of the first transistor, and wherein implanting the substrate under the gate region of the second transistor adjusts a threshold voltage of the second transistor.
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Mistry, K., et al., “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging”, IEDM 2007, pp. 247-250 (Intel).
Burnett James D.
Herr Lawrence N.
Hoefler Alexander
Freescale Semiconductor Inc.
Hill Susan C.
Stark Jarrett J
Vo Kim-Marie
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