Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-02
2003-05-20
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000, C438S636000, C438S643000, C438S770000
Reexamination Certificate
active
06566263
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the use of high density plasma (HDP) chemical vapor deposition (CVD) oxide as intermetal dielectric layers (IMD), and specifically to the use of HDP CVD IMD oxide layers for high aspect ratio design rule for 0.25 to 0.15 &mgr;m technology.
BACKGROUND OF THE INVENTION
High density plasma (HDP) chemical vapor deposition (CVD) oxide has been used as an intermetal dielectric layer (IMD) and passivation materials due to its good gap filling capability. This holds true even for HDP fluorinated silica glass (FSG).
HDP CVD combines sputtering and depositing processes. The gap fill capability is influenced under the sputtering action: seams are found under a low sputter; and metal clipping is found under a high sputter.
However, in devices with high aspect ratio design rule for 0.25 to −0.15 &mgr;m technology, metal voids were observed in metal lines over which the HDP CVD oxide IMD or passivation layers were formed. Such metal voids cause not only metal line off and serious metal electron migration, but also reliability failures.
U.S. Pat. No. 6.030,881 to Papasouliotis et al. describes forming an HDP CVD layer over an aluminum (Al) line.
U.S. Pat. No. 6,008,120 to Lee describes a process for forming an FSG layer over an Al line.
U.S. Pat. No. 5,872,058 to Van Cleemput et al. describes forming an HDP CVD layer over an Al line.
U.S. Pat. No. 6,035,803 to Robles et al. describes a fluorinated carbon film process.
U.S. Pat. No. 5,759,635 to Logan describes a fluorocarbon polymer PECVD process for a low-k layer.
The article “A Mechanism of Stress-induced Metal Void in narrow Aluminum-based Metallization with the HDP CVD oxide dielectric,” Soo Geun Lee et al., IEEE, Jun., 1999, pp. 99-149 to 99-151, proposes a mechanism by which metal voids form when an HDP CVD oxide IMD layer is formed over aluminum (Al) metal lines in devices with 0.25 &mgr;m rule. Factors affecting formation of metal voids were: (1) the deposition temperature of the HDP CVD oxide; (2) the metal layer structure; and (3) the line width. Decreasing the deposition temperature of the HDP CVD oxide reduced formation of the metal voids but occurred slightly at metal pitches lower than 0.75 &mgr;m. When TiN replaced Ti in glue and capping layers for Al metal lines, no metal voids were observed.
From the experimental results, it is suggested that the hydrostatic stress due to the reaction between the Ti and Al at the high temperature HDP CVD oxide deposition is the major driving force for metal void formation. Probability of metal void formation increases rapidly with the HDP CVD oxide formation temperature due to higher induced stress and faster diffusion at higher temperatures.
Annealing at 450° C. for 30 minutes after metal patterning eliminated void formation at 0.7 &mgr;m and 0.64 &mgr;m pitch metal lines. Also, when the backside helium (He) pressure was increased from the normal condition of 4.5 Torr inner/9 Torr outer to 7.0 Torr inner/10.0 Torr outer, the density of void formation was slightly reduced. At 0.8 &mgr;m pitch of metal pattern, no metal void was observed at RF bias power of 2000 W and 1600 W. However, when the metal pitches were decreased to 0.7 &mgr;m and 0.64 &mgr;m, metal voids formed at this lower RF bias power.
The article “Cu Behaviors Induced by Aging and Their Effects on Electromigration Resistance on Al-Cu Lines,” Takeshi Nogami et al., American Institute of Physics, 1996, pp. 198-213 describes an experimental procedure whereby annealed films were subjected a 250° C. aging treatment, to enhance thermal diffusion of Cu atoms in the grains, and studied to determine the role of segregated Cu atoms at grain boundaries. The role of the preferential diffusion of Cu was studied through comparison of time-to-failure's (TTF's) between treated AlSiCu and AlSi lines. A new model was proposed for understanding the electromagnetic (EM) resistance improvement by adding Cu atoms and the aging treatment that includes the role of the preferential diffusion of Cu atoms along the grain boundary and the role of the segregated Cu atoms.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of eliminating voids in metal lines.
Another object of the present invention to provide a method of eliminating voids in aluminum based metal lines down to 0.25 &mgr;m design rule technology.
Yet another object of the present invention is to provide a method of eliminating voids in aluminum based metal lines down to 0.15 &mgr;m design rule technology.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having metal lines formed thereon to form a metal line structure is provided. The metal lines having exposed sidewalls. The metal line structure is treated with N
2
O to form a layer of Al
2
O
3
on each of the metal line exposed sidewalls to form a N
2
O treated metal line structure. An HDP CVD oxide layer is formed over the N
2
O treated metal line structure to form a resulting metal line structure. Whereby the resulting metal line structure is free of metal voids.
REFERENCES:
patent: 5759635 (1998-06-01), Logan
patent: 5811326 (1998-09-01), Yamamoto
patent: 5872058 (1999-02-01), Van Cleemput et al.
patent: 5998303 (1999-12-01), Sato
patent: 6008120 (1999-12-01), Lee
patent: 6030881 (2000-02-01), Papasouliotis et al.
patent: 6035803 (2000-03-01), Robles et al.
patent: 6171947 (2001-01-01), Pangrle et al.
“A Mechanism of Stress-Induced Metal Void in Narrow Aluminum-Based Metallization with the HDP CVD Oxide Dielectric,” Soo Geun Lee et al., IEEE, Jun., 1999, pp. 99-149 to 99-151.
“Cu Behaviors Induced by Aging and Their Effects on Electromigration Resistance on Al-Cu Lines,” Takeshi Nogami et al., American Institute of Physics, 1996, pp. 198-213.
Ger Teh-Wei
Hung Mong-Chi
Wang Ming-Tsong
Ackerman Stephen B.
Nguyen Ha Tran
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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