Method of forming an ESD protection device

Details Method of forming an ESD protection device Method of forming an ESD protection device

2000-01-21

2001-04-17

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S306000, C438S527000, C438S529000, C257S357000

Reexamination Certificate

active

06218226

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming an ESD protection device, more particularly, to a method of forming an ESD protection device with low trigger voltage and small junction capacitance, but without adding any extra mask layer into the conventional CMOS process.
2. Description of the Prior Art
The input signals to a MOS IC are fed to the gate electrodes of MOS transistors. If the voltage applied to the gate insulator becomes excessive, the gate oxide will be broken down. The dielectric breakdown strength of SiO
2
is approximately in the range between 1E7 to 2E7 V/cm. According to a MOS device manufactured by means of the deep-submicron technology (such as 0.18 um technology), the gate oxide has a thickness only about 40 Å and thus will not tolerate to a voltage greater than 8V without being broken down. Although the thinner gate oxide is well in excess of the normal operating voltages of 2.5-V or 3.3-V integrated circuits, a much larger voltage (as high as 2000 V) may be impressed upon the inputs to the circuits during either human-operators or mechanical handling operations. When such a high voltage is applied to the pins of an IC package, its discharge (referred to as electrostatic discharge; ESD) can cause serious damage on the gate oxide of the devices. The ESD event may cause sufficient damage to produce immediate destruction of the device, or it may weaken the oxide strength. Therefore, all pins of MOS ICs must be provided with on-chip ESD protection circuits to prevent such voltages from damaging the MOS gates.
Accordingly, before an ESD applies to the interior devices and damages their gate dielectric, the ESD protection devices have to work and bypass the ESD current. Generally, the breakdown voltage of the PN junction is a key parameter to determine the performance of an ESD protection device. The gate dielectric of integrated circuits is getting thinner in the deep-submicron era, so the breakdown voltage of IC's interior devices is getting lower. Accordingly, it is necessary to reduce the PN-junction's breakdown voltage of the ESD protection devices in order to protect the interior devices before their gate dielectrics are damaged. Therefore, it is a fairly important issue for IC industries to reduce the PN-junction's breakdown voltage of the ESD protection devices.
There are two kinds of PN-junction breakdown, i.e. Zener Breakdown and Avalanche Breakdown. Generally, the Zener Breakdown is used for breakdown mechanism of the ESD protection devices. Zener Breakdown occurs when a reversed bias is strong enough so that the electrons in the valence band of the p-type semiconductor approaching the forbidden gap can tunnel through the forbidden region and appear at the same energy in the conduction band of the n-type semiconductor. Since the probability of transmission of an electron through the barrier is a function of the thickness of the barrier, tunneling is only significant in highly doped material in which the fields are high and the depletion region is narrow. According to some prior arts, an extra step of ESD protection ion-implantation is performed to raise the doping concentration. For example, United Microelectronics Corp. in U.S. Pat. No. 5,585,299 disclosed a method of forming an ESD protection devices, in which an extra step of ESD protection ion-implantation with high energy and high dose is performed to raise the doping concentration and deepen the PN junction. The implantation is performed under the situation that there is no dielectric spacer on the sidewall of the MOS transistor, so that the doping profile of the ion implantation envelopes the LDD (Lightly Doped Drain). However, this process not only needs an extra photo mask for photolithography process, but also increases the junction capacitance so that the transmission speed for input signals becomes much slower.
In order to promote the response speed of the ESD protection devices, United Microelectronics Corp. in U.S. Pat. No. 5,559,352 disclosed a method of forming an ESD protection devices, in which an extra step of P
+
ESD protection implantation with high energy and high dose is performed under the source/drain contacts to lower the breakdown voltage. However, this method needs an extra mask layer to identify the region for ESD implantation.
SUMMARY OF THE INVENTION
Therefore, an object of this invention is to provide a method of forming an ESD protection device.
It is another object of this invention is to provide a method of forming an ESD protection device with low breakdown voltage and low junction capacitance.
The present invention relates to the method of forming an ESD protection device. According to the present invention, an NMOS transistor is formed, and a P
+
ESD protection implantation is applied to reduce the breakdown voltage of PN junction; furthermore, extra N-wells are formed in the source/drain regions of the NMOS transistor to further reduce the junction capacitance. Firstly, a P-well, N-wells, and isolations are formed in a semiconductor substrate. The N-wells are the key features of the present invention in that the design and layout of the photo mask are amended so that N-wells are also formed in a part of the source/drain regions of the NMOS transistor. As a result, the demand of reducing junction capacitance is achieved without adding any photo mask.
Next, a MOS transistor is formed by means of conventional technology. The MOS transistor comprises a gate dielectric layer, a gate electrode, source/drain regions, lightly doped source/drain regions, insulator spacers, and a nitride capping layer.
A key feature of this present invention is that the ESD protection regions are formed under the source/drain regions by means of a P
+
ESD protection implantation to form a heavily-doped PN junction with relatively low breakdown voltage and quick response speed, so as to achieve the purpose of protecting the interior devices. Furthermore, due to adding the N-wells in the NMOS transistor according to the present invention, the area of high-doped PN junction is largely decreased so as to reduce the total junction capacitance on the drain of the NMOS devices.


REFERENCES:
patent: 5545909 (1996-08-01), Williams et al.
patent: 5554544 (1996-09-01), Hsu
patent: 5559352 (1996-09-01), Hsue et al.
patent: 5585299 (1996-12-01), Hsu
patent: 5744841 (1998-04-01), Gilbert et al.
patent: 6040603 (2000-03-01), Yang
S. Wolf, Silicon Processing for the VLSI Era, vol. 1, Lattice Press: Sunset Beach, CA, pp. 280-283, 1986.*
Gilbert, et al. “(Performance improvement of a thick field oxide EDS protection circuit by halo implant” IEEE Proceedings on Custom Integrated Circuits Conf., pp. 35-38, May 1997.

Affiliated with

Also associated with

Rating

Method of forming an ESD protection device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming an ESD protection device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming an ESD protection device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2552651