Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-01-14
2004-09-07
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S279000, C438S301000
Reexamination Certificate
active
06787419
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming an embedded memory, and more particularly, a method of forming an embedded memory having a flash memory structure.
2. Description of the Prior Art
With increasing integration, the present trend of manufacturing semiconductor integrated circuits is to integrate memory cell arrays and other circuit elements, such as a high-speed logic circuit element, onto a single chip. An embedded memory composed of memory cell arrays and logic circuits significantly reduces circuit area and increases the signal processing speed.
Please refer to
FIG. 1
to FIG.
5
.
FIG. 1
to
FIG. 5
are cross-sectional diagrams of a prior art method for manufacturing a metal-oxide-semiconductor (MOS) transistor of an embedded memory on a semiconductor wafer
10
. As shown in FIG.
1
. The semiconductor wafer
10
comprises a silicon substrate
12
defined with a memory array region
20
and a periphery circuit region
30
. The memory array region
20
contains at least a first doped area
16
, and the periphery circuit region
30
contains at least a second doped area
18
and a third doped area
19
. Each area is separated by several shallow trench isolation (STI) structures
14
.
As shown in
FIG. 1
, a bottom oxide
21
, a silicon nitride layer
22
, and a top oxide layer
24
are first formed on the surface of the semiconductor wafer
10
sequentially according to the conventional method of forming an embedded memory. These three layers are also called an oxide-nitride-oxide (ONO) layer
26
. As shown in
FIG. 2
, a first photo-etching process is next performed to remove the ONO layer
26
in the peripheral circuit region
30
and to strip the residual photoresist layer on the surface of the semiconductor wafer
10
and the native oxide layer on the surface of the peripheral circuit region
30
. A thermal oxidization process is then performed to form at least a gate oxide layer
28
on surface of the peripheral circuit region
30
. As shown in
FIG. 3
, a chemical vapor deposition (CVD) process is performed to form a polysilicon layer
32
covering the memory array region
20
and the peripheral circuit region
30
.
Thereafter, a second photo-etching process is performed to pattern the polysilicon layer
32
for forming a control gate of each NROM in the memory array region
20
and gate structures of each MOS transistor in the peripheral circuit region
30
. As shown in
FIG. 4
, a first gate
34
is formed in the memory array region
20
and a second gate
36
and a third gate
38
are formed in the peripheral circuit region
30
. As shown in
FIG. 5
, a plurality of ion implantation processes are performed with proper masks to form corresponding doped regions surrounding the first gate
34
, the second gate
36
, and the third gate
38
, which serve as a source or a drain of each MOS transistor.
Since the NROM uses the nitride layer in the ONO layer as a charge trapping medium, electrons injected to the nitride layer through the tunneling of the MOS transistor are trapped therein due to the highly dense nitride layer. Thus, a various concentration distribution is formed and the distribution of the threshold voltage is thereby modified so as to achieve a function of memorizing. It is understood that the NROM is very sensitive to the quality of the ONO layers. However, in the conventional method of forming an embedded memory, a plurality of cleaning, etching, or thermal oxidizing processes are needed for fabricating circuit elements in the peripheral circuit region, such as forming the gate oxide layer on the surface of the peripheral circuit region. These processes cause the thickness loss of the ONO layer on the surface of the memory array region or deteriorate the quality of the ONO layer, significantly affecting the electric performance of the NROM and reducing the stability and reliability of the embedded memory.
Consequently, there is a strong need to develop a method of forming an embedded memory to solve the problem in the prior art method and improve the reliability of products.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a method of manufacturing a MOS transistor of an embedded memory to solve the aforementioned problem.
It is another objective of the claimed invention to provide a method of forming a SONOS non-volatile memory, such as an electrically erasable programmable read-only memory (EEPROM) or a flash memory.
In the preferred embodiment of the claimed invention, a method of forming a MOS transistor of an embedded memory is disclosed. First, a semiconductor wafer is provided. The semiconductor wafer comprises a substrate defined with a first region and a second region. Next, an ONO layer, a first silicon layer, and a silicon nitride layer are formed on the surface of the semiconductor wafer in turn. Then, a first photo-etching process is performed to remove the ONO layer, the first silicon layer, and the silicon nitride layer on the second region. After that, at least one gate oxide layer is formed on the second region. A second silicon layer is then formed on the surface of the semiconductor wafer. Thereafter, a second photo-etching process is followed to remove the second silicon layer and the silicon nitride layer on the first region. After forming at least a third silicon layer covering the semiconductor wafer, a photo-etching process is then performed to form a gate structure of each MOS transistor in the first region and the second region respectively. A plurality of ion implantation processes are performed in the first region to form a source and a drain of each MOS transistor in the first region. Then, a plurality of ion implantation processes are performed in the second region to form a source and a drain of each MOS transistor in the second region.
It is an advantage of the claimed invention that a silicon layer and a dielectric layer are formed on the ONO layer to protect the ONO layer from being affected by the following process so as to improve the reliability of the embedded memory significantly.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 6015732 (2000-01-01), Williamson et al.
patent: 6417086 (2002-07-01), Osari
patent: 6455374 (2002-09-01), Lee et al.
Chen Chung-Yi
Chou Jih-Wen
Chu Chih-Hsun
Brewster William M.
Coleman W. David
e-Memory Technology, Inc.
Hsu Winston
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