Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-05-17
2004-03-09
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S720000, C438S724000
Reexamination Certificate
active
06703312
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to photolithographic patterning of a semiconductor substrate and more specifically to a method for of manufacturing logic and DRAM critical gatelengths using lithographic critical dimension imaging.
BACKGROUND OF THE INVENTION
Logic based embedded dynamic random access memories (hereinafter DRAMs) requires that the DRAM be embedded in a logic chip without adversely affecting the performance of logic devices thereon. This is a necessity for offering logic library design platforms which include embedded DRAM macros. As the scale of integration increases, device feature sizes are reduced, requiring devices to be fabricated with ever smaller gatelengths, such that some gatelengths required for logic today can no longer be achieved by photolithography alone.
When very small gatelengths are desired (less than 0.1 um), one current method of attaining the reduced size is to print a larger photoresist pattern and then to trim the feature during the mask open process. Doing so requires that pattern size on the reticle be larger by at the least the trim amount (for example by 0.05 um), e.g. a reticle pattern size of 0.14 um for printing a 0.14 um resist pattern which is then trimmed during a mask open process to 0.09 um.
However, the printing of larger features and trimming by mask open cannot be done for very closely spaced line patterns of the DRAM array (e.g. gate conductors (GC) in a planar device DRAM; or polysilicon wordlines in a DRAM array having vertical devices (both of which are hereinafter referred to as gate conductors (GCs)). The problem results from GC pitch limitations in the DRAM array. To illustrate, in a DRAM array which requires a GC pitch of 0.29 um, GC linewidth may be set to 0.15 um, while the space between GCs may be set to 0.14 um. If GCs of the DRAM array were patterned by the same process of printing large features and trimming them, as used for logic gates, the desired GC pitch could not be achieved. To further illustrate, when the required GC linewidth is 0.15 um and the required GC spacing is 0.14 um, the required printed feature sizes before trimming would be GC linewidth of 0.20 um and GC spacing of 0.09. However, such line/space photoresist patterns cannot be printed using available photolithography because the linewidth/space ratio is too high for the feature size. The problem here, therefore, becomes not so much the printing of the photoresist but rather the ability to print the required line/space patterns in both the logic and DRAM array of the chip, simultaneously. One can imagine that this problem can only become worse in future generation technologies when feature sizes are reduced even further.
Another problem is achieving desired gatelengths simultaneously, while maintaining processing tolerances for the different field effect transistor types of both logic and DRAM. Logic chips must meet aggressive requirements for across chip line width variation (hereinafter ACLV), as dictated by the technology generation. The lithography process window to fulfill logic ACLV requirements is extremely small. For logic-based embedded DRAM chip fabrication, the DRAM FET gatelength requirements add another degree of critical dimension control, which results in minimum to nonexistent lithographic process windows. In order to make both the logic FET and DRAM FET gatelengths on target, the solutions often require many iterations of design data changes and mask rebuilds, which affect the overall cost and timeliness of development cycles. A new solution is needed to achieve desired gatelengths in both the logic FET and DRAM FET of logic chips with embedded DRAM.
SUMMARY OF THE INVENTION
Accordingly, in the present invention a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Then, a photoresist layer thereover is patterned using a critical dimension mask to define photoresist patterns in the first and second portions, which are then used to pattern the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. The feature layer is then simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.
In a preferred embodiment of the invention, a method is provided for defining GC and polysilicon line features of different gatelengths in the respective logic and embedded DRAM portions of a combined logic and embedded DRAM chip, without requiring such features of the logic portion and the DRAM array portion to be patterned by separate critical dimension masks. In an embodiment described herein, very small gatelength features are formed by this method in the logic portion, while longer gatelength features are formed in the array portion of the chip at the same time.
In a preferred embodiment of the invention, a layer of gate conductor material such as polysilicon is deposited on a semiconductor substrate, after which a layer of oxide is deposited thereover. Then, using a single critical dimension mask, a photoresist is applied and patterned having the same linewidths in both logic and array portions of the substrate. Next, a mask open process is performed to etch and trim the underlying oxide layer with the resist pattern in both logic and array portions of the substrate, resulting in oxide patterns. Spacers are then formed on sidewalls of the oxide patterns. Then, a block mask is used to protect the array portion of the substrate while the sidewall spacers are removed from the logic portion. Preferably, an additional hardmask is deposited over the oxide/spacer patterns to further protect spacers in the array portion while spacers are removed from the logic portion via, for example, a selective wet etch technique. The underlying gate conductor material is then etched, using the oxide patterns in the logic portion of the substrate as a hardmask, and using the combined oxide/spacer patterns in the array portion as a hardmask. In this manner, gate conductors having different gatelengths are simultaneously defined in respective logic and array portions of the substrate using only one critical dimension mask. Further gate conductor processing then proceeds in any of several ways as is well known to those skilled in the art.
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patent: 6407420 (2002-06-01), Yamanaka et al.
patent: 6586303 (2003-07-01), Wu
Golz John Walter
Khan Babar
Liu Joyce C.
Waskiewicz Christopher Joseph
Wu Teresa Jacqueline
Blecker Ira D.
Chen Kin-Chan
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