Method of forming a via

Details Method of forming a via Method of forming a via

2007-11-30

2010-06-29

Pham, Thanhha (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S655000, C257SE21619

Reexamination Certificate

active

07745298

ABSTRACT:
A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.

REFERENCES:
patent: 6165880 (2000-12-01), Yaung et al.
patent: 6184073 (2001-02-01), Lage et al.
patent: 6369420 (2002-04-01), Yeh et al.
patent: 6737308 (2004-05-01), Kim
patent: 2006/0099729 (2006-05-01), Yang

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