Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-11
2003-04-22
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S243000, C438S248000, C438S386000, C438S433000
Reexamination Certificate
active
06551875
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method of manufacturing a deep trench capacitor with or without a vertical transistor thereon. More particularly, the present invention relates to a method for forming a uniform collar oxide layer over an upper portion of a trench sidewall by local oxidation.
2. Description of the Related Art
DRAM is memory capable of reading and writing information. Each DRAM cell needs only one transistor and one capacitor, therefore, it is easy to achieve higher integration to make it broadly applicable to computers and electric equipment. A trench capacitor, which is formed in the semiconductor silicon substrate, is one of the most commonly used capacitors. With the enhancement of the depth of the trench capacitor in the semiconductor silicon substrate, the surface area of the trench capacitor is increased, so that the capacitance is increased.
In order to enhance the density of DRAM cells to increase the total capacitance, the transistor is disposed vertically and the vertical transistor located over the deep trench capacitor replaces the traditional plane-stacked transistor. Before fabricating the trench capacitor, local oxidation is executed as described hereafter. An oxide layer and a nitride layer are conformally deposited over a trench which extends into the semiconductor substrate. A photoresist is formed over the nitride layer, then the photoresist is removed until an upper portion of the trench sidewall having the oxide layer and the nitride layer thereon is exposed. The exposed nitride layer is removed, followed by the oxide layer. The remaining photoresist is then removed. Local oxidation is performed to oxidize the exposed, upper portion trench sidewall and to form a collar oxide layer.
It should be noted that the exposed surface of the trench shows two kinds of crystallographic orientations: (110) orientation and (100) orientation. The oxidation rate varies with orientation, resulting in a disuniform collar oxide layer formed in the trench with unexpected electrical properties. In general, the oxidation rate in (110) is larger then that in (100).
SUMMARY OF THE INVENTION
The present invention provides a method of forming a uniform collar oxide layer over an upper portion of a vertically extending sidewall of a trench extending into a semiconductor substrate. According to one aspect of the invention, the method involves the following steps. A layer of covering material is formed on a substantially vertically extending sidewall of a trench which extends into a semiconductor substrate. The layer of covering material is partially removed over only a portion of the sidewall to expose an upper region. The surface of the exposed region is treated to make the (110) and (100) orientations have the same oxidation rates by ion implantation. A uniform collar oxide layer grows over the exposed portion by local oxidation of the upper region.
According to another aspect of the invention, a method is provided for forming a uniform collar oxide layer over an upper portion of a trench sidewall with (110) and (100) orientations. This alternate method involves the following steps. A conformal mask layer is deposited on a substantially vertically extending sidewall of a trench. The trench is filled with a resist material, and the resist material is etched a predetermined depth from the upper surface of the substrate to the upper surface of the remaining resist, thereby removing a portion of the mask layer from an upper portion of the sidewall in order to space the substrate a set distance from an upper surface of the substrate. Ion implantation is conducted to treat the (110) and (100) orientations existing on the trench sidewall to have the same oxidation rates. A uniform collar oxide layer is formed over the exposed portion by local oxidation of the upper region.
In accordance with the present invention, the dopant used in the ion implantation process can be an oxidation-suppressed dopant or an oxidation-enhanced dopant. In the former case, the dopant can be nitrogen (N
2
), neon (Ne), argon (Ar), xenon (Xe) or others. In the latter case, the dopant can be oxygen or another. The tilt angle &thgr; of the wafer used in the ion implantation process depends on the width (w) of the trench and the depth (d) of the exposed trench sidewall, and is (tan
−1
w/d)±0.5°, preferably between about 7° and about 45°. The ion implanting energy is below 200 keV. The dosage used is between 1×10
12
and 5×10
16
.
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patent: 6362040 (2002-03-01), Tews et al.
Duong Khanh B.
Nanya Technology Corporation
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