Method of forming a transistor structure

Details Method of forming a transistor structure Method of forming a transistor structure

1997-09-08

2001-07-17

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S262000, C438S263000, C438S266000

Reexamination Certificate

active

06261902

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a semiconductor device in which polysilicon is used to form source and drain regions in an initial process step so as to reduce resistance of bit lines and minimize a junction capacitance and thus improve its reliability, and a method for fabricating the same.
2. Discussion of the Related Art Due to buried N
+
layers(hereinafter referred to as BN
+
layer), which is used in flash EEPROM cells and mask ROM cells, it is possible to make virtual ground, and the number of contact holes is diminished to reduce sizes of chips. Source and drain regions are commonly formed in a final process step in a case a semiconductor device is fabricated using BN
+
layers.
A conventional method for fabricating a semiconductor device will be described with reference to
FIGS. 1A
to
1
C which are cross-sectional views showing process steps of a method for fabricating a semiconductor device.
First, a photoresist film is coated on a semiconductor substrate
11
or a p well as shown in FIG.
1
A. In this case, instead of a photoresist film
13
alone being coated, an insulating layer is first deposited on a semicondutor substrate
11
and then a photoresist film
13
is coated on the insulating layer.
Next, as shown in
FIG. 1B
, the photoresist film
13
over placements of BN
+
layers is patterned by exposure and development processes. N
+
heavily doped impurity ions are implanted into the semiconductor substrate
11
by using the photoresist pattern
13
as a mask.
Subsequently, the remaining photoresist film
13
is removed as shown in FIG.
1
C. Then an annealing process is performed to grow a gate oxide layer
15
on the semiconductor substrate
11
and simultaneously form BN
+
layers
17
. At this time, the BN
+
layers
17
function as source and drain regions. The gate oxide layer
15
is thicker on the BN
+
layers than on the semiconductor substrate
11
because the BN
+
layers have a high concentration of impurity ions.
According to a conventional method for fabricating a semiconductor device, source and drain regions are formed in an initial process step and gate electrodes are formed right over the source and drain regions so that it can be possible to make virtual ground and the number of contact holes in a cell is minimized to reduce the area of a chip.
However, it has following problems. There is a reduced a voltage applied to bitlines in contact with BN
+
layers due to a resistance of the BN
+
layers. Moreover, since a junction area of the BN
+
layers and a semiconductor substrate increases and thus a junction capacitance on the junction area increases, operational speed of the semiconductor device is lowered.
SUMMERY OF THE INVENTION
Therefore, the present invention is directed to a structure of a semiconductor device and a method for fabricating the same that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the invention is to provide a method for fabricating a semiconductor device in which BN
+
layers are formed of doped polysilicon to be used as source and drain regions so as to reduce a resistance of bitlines and minimize a junction capacitance and thus increase its reliability.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor device includes a semiconductor substrate, trenches formed in predetermined areas of the semiconductor substrate, an insualting layer formed beneath a surface of each of the trenches to have a recess, a polysilicon layer formed on the insualting layer in the trench, source and drain regions formed at both sides of the polysilicon layer beneath a surface of the semiconductor substrate, and gates formed over the semiconductor substrate.
In another aspect of the present invention, a method for fabricating a semiconductor device includes the steps of forming trenches in predetermined areas of a semiconductor substrate, forming a first polysilicon layer doped by impurity ions in each of the trenches, diffusing the impurity ions in the first polysilicon layer so as to form source and drain regions at both sides of each of the trenches, and forming a second polysilicon layer on the entire surface and then patterning the second polysilicon layer to form gates.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: H204 (1987-02-01), Oh et al.
patent: 4331968 (1982-05-01), Gosney, Jr. et al.
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4419150 (1983-12-01), Soclof
patent: 4569701 (1986-02-01), Oh
patent: 4676847 (1987-06-01), Lin
patent: 4814840 (1989-03-01), Kameda
patent: 4833098 (1989-05-01), Kato
patent: 4839309 (1989-06-01), Easter et al.
patent: 5045490 (1991-09-01), Esquivel et al.
patent: 5086007 (1992-02-01), Ueno
patent: 5324684 (1994-06-01), Kermani et al.
patent: 5406111 (1995-04-01), Sun
patent: 5429970 (1995-07-01), Hong
patent: 5460987 (1995-10-01), Wen et al.
patent: 5605852 (1997-02-01), Bencuya
patent: 5707897 (1998-01-01), Lee et al.
patent: 5773343 (1998-06-01), Lee et al.
patent: 5882971 (1999-03-01), Wen
N. Ajika et al., “A 5 Volt Only 16M Bit Flash Eeprom Cell With a Simple Stacked Gate Structure”, LSI Research and Development Laboratories, Mitsubishi Electronic Corporation, reprint of IEDM Tech. Digest, pp. 115-118, 1990.

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