Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2002-12-31
2004-05-04
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S296000, C438S503000
Reexamination Certificate
active
06730576
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and in particular to semiconductor devices that incorporate strained silicon.
2. Related Technology
The continuous demand for improved performance in electronic devices has been addressed through advances in silicon processing and device technologies directed toward reduction in the size of individual semiconductor circuit components. However, economic and physical constraints are making continued reduction of device sizes more difficult, and so alternative solutions are being sought to allow increases in device performance to continue.
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of silicon so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of recent attention is the use of silicon material to which a tensile strain is applied. “Strained” silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is generally more widely spaced than a pure silicon lattice as a result of the presence of the larger germanium atoms in the lattice. Because the atoms of the silicon lattice align with the more widely spread silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
An example of a MOSFET using a strained silicon layer is shown in FIG.
1
. The MOSFET is fabricated on a substrate comprising a silicon germanium layer
10
on which is formed an epitaxial layer of strained silicon
12
. The MOSFET uses conventional MOSFET structures including deep source and drain regions
14
, shallow source and drain extensions
16
, a gate oxide layer
18
, a gate
20
surrounded by spacers
22
,
24
, silicide source and drain contacts
26
, a silicide gate contact
28
, and shallow trench isolations
30
. The channel region of the MOSFET includes the strained silicon material, which provides enhanced carrier mobility between the source and drain.
While the theoretical advantages of strained silicon are promising, the fabrication and processing of strained silicon presents a number of problems. One problem is the formation of “misfit dislocations” in the strained silicon as the result of temperature changes. Misfit dislocations are dislocations in the silicon lattice that effectively release the strain applied to the silicon lattice. Misfit dislocations are primarily caused by mismatch between the strained silicon lattice and the lattice of the underlying silicon germanium supporting layer. The amount of misfit dislocations in a strained silicon layer may increase as the result of thermal factors. One instance in which misfit dislocations may be caused by thermal factors is during cooling after deposition of a strained silicon layer. Another instance in which misfit dislocations may occur is during exposure to high temperatures, e.g. 1000 degrees C. and higher, such as during formation of shallow trench isolations. Such high temperatures are believed to cause depletion of the germanium content of the silicon germanium substrate, leading to formation of misfit dislocations in the overlying strained silicon. The rate of formation of misfit dislocations rises exponentially with increases in temperature.
has been determined that a strained silicon layer has a critical thickness, above which misfit dislocations become significantly more likely to occur. The critical thickness depends on the amount of tensile strain applied to the silicon lattice, and thus on the germanium content of the underlying silicon germanium layer. For example, it has been determined that a silicon germanium layer having approximately 20% germanium content can support a critical thickness of approximately 200 Angstroms without the risk of significant misfit dislocations, whereas a silicon germanium layer having approximately 30% germanium content can support a critical thickness of only approximately 80 Angstroms.
Therefore the application of current strained silicon technology to MOSFET design is hampered by conflicting limitations, in that strained silicon carrier mobility is enhanced by an increase in the germanium content of the underlying layer, yet the critical thickness of the strained silicon is reduced by an increase of the germanium content of the underlying layer. These conflicts make practical applications difficult to achieve. For example, it has been determined empirically that at least approximately 70 Angstroms of strained silicon are required to provide a meaningful improvement in MOSFET performance. However, in order to account for consumption of silicon during processing, a layer of approximately double that thickness must be formed initially, and to avoid misfit dislocation in a layer of such thickness, the germanium content of the underlying layer must be restricted to approximately 20%. The resulting strain applied to the strained silicon layer has been found to have relatively little effect on hole mobility, and therefore it is difficult to provide a meaningful application of strained silicon in PMOS devices. In addition to the foregoing considerations, the tensile strain of the strained silicon layer and hence its carrier mobility may be further degraded through the formation of misfit dislocations caused by both the increases and the decreases in temperature that are typically encountered during processing, such as during formation of shallow trench isolations. Therefore, while the limiting factors of strained silicon technology can be balanced to achieve limited carrier mobility enhancement in some applications, current technology does not offer a way to impart enough strain to produce significant carrier mobility enhancement without also introducing mobility-reducing defects and strain relaxation.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a strained silicon layer having a thickness greater than the conventional critical thickness yet not having the amount of misfit dislocations that are characteristic of a strained silicon layer having a thickness greater than the conventional critical thickness.
It is another object of the present invention to provide a MOSFET device that incorporates a strained silicon layer having a thickness greater than the conventional critical thickness.
In accordance with embodiments of the invention, shallow trench isolations are formed in a silicon germanium layer prior to growth of a strained silicon layer on the silicon germanium layer. Subsequently, a strained silicon layer is fabricated on the layer of silicon germanium and a second silicon germanium layer is formed over the layer of strained silicon in a
Besser Paul R.
Goo Jung-Suk
Ngo Minh V.
Paton Eric N.
Wang Haihong
Advanced Micro Devices , Inc.
Foley & Lardner LLP
Wilczewski Mary
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