Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-01
2001-10-02
Fahmy, Jr., Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S227000, C438S262000, C438S278000
Reexamination Certificate
active
06297102
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method of combining PLDD (p-type lightly doped drain) implant and surface implant for ROM cell surface implant region to reduce processing steps and simplify the process.
2) Description of the Prior Art
Currently, CMOS ROM cells require numerous photolithograpy and implant steps for NLDD (n-type lightly doped source and drain regions), PLDD (p-type lightly doped source and drain regions), n-type and p-type source and drain region implants, and surface implants for ROM cell surface implant region. These photolithography and implant steps add cost and processing time as well as increasing opportunities for loss Is of cells due to processing variations. A need exists to reduce the number of processing steps, thereby reducing cost and processing time and improving process yield.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,538,914 (Chiu et al.) teaches a LDD method for a ROM.
U.S. Pat. No. 5,700,729 (Lee et al.) discloses a masked gate MOS source and drain ion implant method including a PLDD.
U.S. Pat. No. 5,830,795 (Mehta et al.) recites a simplified masking process for a logic device including PLDD and Vt ion implant steps.
U.S. Pat. No. 5,843,816 (Liaw et al.) shows a process for a SRAM using a PLDD implant step.
U.S. Pat. No. 5,650,341 (Yang et al.) teaches a method for forming a CMOS PLDD and NLDD using a method to reduce masking steps and costs.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for combining a PLDD (p-type lightly doped drain) implant and a surface implant for ROM cell surface implant region.
It is an object of the present invention to provide a method for combining a PLDD (p-type lightly doped drain) implant and a surface implant for ROM cell surface implant region in a flat cell mask ROM process.
It is another object of the present invention to provide a method for forming a ROM cell surface implant region using a PLDD implant.
It is another object of the present invention to provide a method for forming a CMOS ROM cell which reduces the number of processing steps.
It is yet another object of the present invention to provide a method for forming a CMOS ROM cell which reduces cycle time and cost.
To accomplish the above objectives, the present invention provides a method for forming a ROM cell surface implant region using a PLDD implant, thereby reducing the number of processing steps required. The method begins by providing a semiconductor structure comprising a substrate having isolation structures thereon, which separate and electrically isolate: a first area having a P-well formed in the substrate and a gate over the substrate; a second area having a N-well formed in the substrate and a gate over the substrate; and a third area having P-well and buried N+ regions formed in the substrate with second isolation structures overlying the buried N+ regions. A photoresist mask is formed exposing the first area, and impurity ions are implanted to form n-type lightly doped source and drain regions. The photoresist mask is removed and a new (PLDD/ROM) photoresist mask is formed exposing the second area and the third area. Impurity ions are implanted to simultaneously form P-type lightly doped source and drain regions and a ROM cell surface implant region. The PLDD/ROM photoresist mask is then removed.
The present invention provides considerable improvement over the prior art. The key advantages of the present invention are that a separate ROM cell photolithography and implant step can be eliminated, thereby reducing processing time and cost, while yield and performance can be maintained.
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Wu Lin-June
You Jyh-Cheng
Ackerman Stephen B.
Eaton Kurt
Fahmy Jr. Wael
Saile George O.
Stoffel William J.
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