Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-11-20
2003-01-07
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S699000, C438S738000, C438S759000, C438S430000
Reexamination Certificate
active
06503848
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to converting a rough top surface of a layer of polysilicon, which is rough due to polysilicon grains, to a smooth top surface.
2. Description of the Prior Art
Polysilicon is a frequently used material in the fabrication of integrated circuits. Usually photolithography steps must be carried out after the layer of polysilicon has been deposited. The top surface of a layer of polysilicon will be rough due to polysilicon grains at the top surface of the layer. As critical dimensions continue to become smaller this roughness due to the polysilicon grains at the surface will impact photolithographic processing.
U.S. Pat. No. 5,631,197 to Yu et al. describes a method for forming a sacrificial planarization layer over a spin on glass layer.
U.S. Pat. No. 6,190,949 to Noguchi et al. describes a method for forming a layer of polysilicon.
U.S. Pat. No. 4,952,274 to Abraham describes a method for planarizing an insulating layer.
U.S. Pat. No. 6,037,251 to Tu et al. describes a method for intermetal dielectric planarization.
U.S. Pat. No. 5,435,888 to Kalnitsky et al. describes a method of planarizing integrated circuit topographies using a first spin-on-glass layer, a layer of low temperature oxide, and a second spin-on-glass layer.
U.S. Pat. No. 5,302,551 to Iranmanesh et al. describes a method for planarizing the surface of an integrated circuit over a metal contact layer.
SUMMARY OF THE INVENTION
The top surface of a layer of polysilicon will have a surface roughness due to the polysilicon grain size.
FIG. 1
shows a layer of polysilicon
16
formed on a substrate
10
showing the rough top surface of the layer of polysilicon
16
. As critical dimensions get smaller it is important to smooth the top surface of the layer of polysilicon so that subsequent photolithographic processing steps will not be affected. Anti-reflective coatings can help avoid the photolithographic problems but the anti-reflective coatings required must be thick and will affect subsequent etching steps.
The substrate
10
shown in
FIG. 1
has a shallow trench filled with a first dielectric
12
formed therein for shallow trench isolation. A layer of second dielectric
14
is formed over the substrate
10
and the first dielectric
12
in the trench. The layer of polysilicon
16
is deposited on the layer of second dielectric
14
. The shallow trench isolation region has slight depressions
18
at the edges of the trench. The top surface
15
of the first dielectric
12
in the trench extends a small distance above the top surface
11
of the substrate. The layer of polysilicon
16
follows the contours of the surface on which it is deposited and has substantially the same thickness over the entire layer of polysilicon.
After the top surface
19
of the layer of polysilicon has been smoothed, it is important that the remaining layer of polysilicon is substantially uniform in thickness over the entire substrate
10
and that the region of the layer of polysilicon over the first dielectric
12
in the trench is substantially the same as over the active region of the substrate
10
. Any difference in thickness of the layer of polysilicon
16
can cause problems in subsequent processing steps, particularly etching steps.
It is a principal objective of at least one embodiment of this invention to provide a method of smoothing the top surface of a layer of polysilicon while maintaining the same thickness of polysilicon over the entire layer of polysilicon.
This objective is achieved by depositing a polymer, such as C
x
F
y
Br
z
, having a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.
In one embodiment the layer of polymer has a thickness large enough so that the top surface of the polymer is more than the critical distance above the peaks of the grains on the top surface of the layer of polysilicon. In this case the polymer can be etched back so that the top surface of the polymer is at least an extended critical distance, which is greater than or equal to the critical distance, above the peaks of the grains on the top surface of the layer of polysilicon using any appropriate etching method. Then the remainder of the layer of polymer and part of the layer of polysilicon are etched away using an etch back method which etches the polymer and polysilicon at the same etch rate.
REFERENCES:
patent: 4952274 (1990-08-01), Abraham
patent: 5302551 (1994-04-01), Iranmanesh et al.
patent: 5320708 (1994-06-01), Kadomura et al.
patent: 5435888 (1995-07-01), Kalnitsky et al.
patent: 5500077 (1996-03-01), Nishibayashi et al.
patent: 5631197 (1997-05-01), Yu et al.
patent: 6037251 (2000-03-01), Tu et al.
patent: 6190949 (2001-02-01), Noguchi et al.
patent: 2000124457 (2000-04-01), None
Chan Bor-Wen
Chiu Yuan-Hung
Lin Huan-Just
Tao Hun-Jan
Ackerman Stephen B.
Pham Long
Pham Thanh
Prescott Larry J.
Saile George O.
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