Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-06
2001-03-20
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S525000, C438S664000, C438S683000
Reexamination Certificate
active
06204132
ABSTRACT:
FIELD OF THE INVENTION
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of forming a silicide region.
BACKGROUND OF THE INVENTION
Titanium silidde has become the most widely-used silicide in the VLSI industry for self-aligned silicide applications because of its combined characteristics of low resistivity, the ability to be self-aligned, and relatively good thermal stability. Although TiSi
2
has certain advantages relative to other silicides, the fact that it is a polymorphic material presents additional problems in its use. Specifically, in typical use TiSi
2
exists as either an orthorhombic base-centered phase having 12 atoms per unit cell and a resistivity of about 60-90 micro-ohm-cm (known in the industry as the C49 phase), or as a more thermodynamically-favored orthorhombic face-centered phase which has 24 atoms per unit cell and a resistivity of about 12-20 micro-ohm-cm (known as the C54 phase). When using the generally-accepted processing conditions for forming titanium silicide, the less-desirable, higher-resistivity C49 phase is formed first. In order to obtain the lower-resistivity C54 phase, a second high-temperature annealing step is required.
A typical set of processing conditions for forming C54 phase titanium silicide include: (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at a temperature about 700° C. or below, (4) selective etching, and (5) a phase transformation anneal at a temperature greater than about 700° C. It is the phase transformation anneal that converts the dominant C49 phase to the C54 phase. The initial formation temperature is kept about 700° C. or below in order to minimize over-spacer bridging. The second transformation anneal is performed after any un-reacted titanium has been selectively removed and is generally performed at temperatures of 50°-200° C. above the formation temperature to insure full transformation to the C54 phase for best control of sheet resistance. However, as device line-widths and silicide film thickness continue to be scaled down, the C49 to C54 transformation becomes more difficult on these narrow structures (such as narrow gate structures) due to the low C54 nucleation density.
It is generally accepted that the C49 phase forms first because of a lower surface energy than that of the C54 phase. In other words, the higher surface energy of C54 phase forms a higher energy barrier to its formation. The second transformation anneal step used in the standard process above provides the additional thermal energy necessary to both overcome the nucleation barrier associated with forming the new surface and growing the crystalline structure of the newly-forming C54 phase. In VLSI applications, if the phase transformation is inhibited or fails to occur uniformly, a degradation in circuit performance is observed. In some higher-performance circuits, the RC delay associated with a poor phase transformation is typically about 5-10 percent.
A significant limitation on the C49-to-C54 phase transformation is a phenomenon known as agglomeration. If the thermal energy used to obtain the phase transformation is excessive, then a morphological degradation of the titanium silicide results, which is commonly referred to as agglomeration. As line-widths and silicide film thickness decrease, the thermal energy required to affect the C49 -to- C54 phase transformation increases, yet the thermal energy level at which the silicide film starts to agglomerate decreases. Thus, there is an ever-shrinking process window for performing this phase transformation, making process control and uniformity more difficult to achieve.
Thus, there is a need for an improved method for forming the C54 phase titanium silicide.
One solution to this problem involves causing at least a portion of the polycrystalline silicon structure to become amorphous. This can be done by subjecting the polycrystalline silicon structure to preamorphization implant (PAI) prior to the deposition of titanium. As is described in a prior patent application assigned to Texas Instruments, Ser. No. 09/110,034 , this PAI can be accomplished by implanting either Ge or As into the polycrystalline structure so as to make it amorphous for at least 10 to 30 nm into the structure.
A problem with this method is that a fairly small percentage of the transistors formed using this method fail. More specifically, some devices will have an on-current versus off-current that is dramatically different from an average device.
SUMMRY OF THE INVENTION
Basically, the instant invention involves a method of performing a PAI which eliminates or reduces the amount of PAI dopant which penetrates through the layer to be silicided (such as a polycrystalline silicon gate structure) and into an underlying dielectric layer (such as a gate dielectric layer) or semiconductor layer (such as a silicon substrate). Preferably, this is accomplished by performing the PAI step at an implantation angle of seven degrees or greater, from the direction perpendicular to the substrate active surface (the surface of the substrate on which the components of the circuit are fabricated), while the wafer is rotated in the x-y plane. This rotation may either be continuously performed as the implantation is done or in discrete steps.
An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate which lies in an x-y plane, the method comprising the steps of: forming a semiconductive structure insulatively disposed over the semiconductor substrate; amorphizing a portion of the conductive structure by introducing an amorphizing substance into the semiconductive structure at an angle, theta, which is greater than seven degrees from a z-axis which is normal to the semiconductor substrate; forming a metal layer on the conductive structure; and wherein the metal layer interacts with the semiconductive structure in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. Preferably, the semiconductive structure is comprised of a material selected from the group consisting of: doped polysilicon, undoped polysilicon, epitaxial silicon, and any combination thereof; and the metal layer is comprised of a material selected from the group consisting of: titanium, Co, W, Mo, nickel, platinum, palladium, and any combination thereof.
In an alternative embodiment, a low temperature anneal step is performed after the step of forming a metal layer on the gate structure. Preferably, the low temperature anneal step is comprised of subjecting the transistor to temperatures in excess of 600 C., and, more preferably, it is comprised of subjecting the transistor to a temperature around 700 to 800 C.
The amorphizing substance is, preferably, comprised of a substance selected from the group consisting of: As, Ge, or any combination thereof. The angle, theta, may be given by:
theta>arctan (L/d)
or by
7°<theta ≦arctan (L′/2d)
where L is the gate length of the transistor, d is the thickness of the semiconductive structure, and L′ is the distance from the edge of one gate structure to the edge of the closest gate structure. Preferably, the angle, theta, is around 25 degrees. The semiconductor substrate is, preferably, rotated in the x-y plane during the step of introducing the amorphizing substance into the semiconductor structure. Preferably, the semiconductor substrate is continuously rotated in the x-y plane during the step of introducing the amorphizing substance into the semiconductor structure, or it is rotated in discrete steps. The step size may be around 90 degrees, or it may be around 45 degrees.
Another embodiment of the instant invention is a method of siliciding a structure comprised of a semiconductive material situated over a semiconductor substrate, the method comprising the steps of: amorphizing a portion of the semiconductive material by introducing an amorphizing substance into the s
Bowles Christopher
Kittl Jorge A.
Brady III Wade James
Pham Long
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Valetti Mark A.
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