Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-28
2001-08-21
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S211000, C438S230000, C438S299000, C438S682000, C438S683000
Reexamination Certificate
active
06277683
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process sequence used to form sidewall spacers, and salicide blocking shapes, using silicon nitride.
(2) Description of Prior Art
The use of complimentary metal oxide semiconductor, (CMOS), devices, for both logic, as well as memory applications, fabricated on the same semiconductor chip, have resulted in increased process complexity, as well as increased cost, for the integrated CMOS devices. The ability to share specific process steps, or sequences, used for each type, logic and memory, can significantly reduce process complexity and cost. For example a Self-ALigned metal silICIDE, (salicide), layer, is used with the high performance, CMOS logic devices, while the salicide layer is not desired for CMOS memory applications. A silicon nitride shape is sometimes used to block salicde formation in the CMOS memory region, while being introduced in the CMOS logic area. The silicon nitride layer used for the salicide blocking shape, can however be the second silicon nitride used in the integration of CMOS logic and memory devices. Prior to formation of heavily doped source/drain regions, for both type devices, sidewall spacers, formed from a first silicon nitride layer, are formed on the sides of gate structures, to prevent gate to substrate leakage or shorts. Since the integrity of the sidewall spacer, as well as the quality of the silicide blocking shape, are paramount, high quality silicon nitride layers, in terms of diffusion barrier, are needed for these functions. Therefore these silicon nitride layers are obtained via a low pressure chemical vapor deposition, (LPCVD), procedure, usually performed at a temperature between about 800 to 900° C., instead of the use of plasma enhanced vapor deposition, (PECVD), silicon nitride layers, obtained at temperatures lower than 800° C.
The use of two, high temperature deposited silicon nitride layers, however can exhaust the thermal budget allotted for the fabrication of the integrated CMOS chip,. in terms of unwanted movement of doping profiles. Therefore a novel process sequence, utilizing only a single silicon nitride layer, for both sidewall spacer, and salicide blocking shape, will be presented, removing one high temperature process, thus preserving the thermal budget. The novel process sequence detailed in this present invention, features definition of a silicon nitride blocking shape, in the CMOS memory region, and the formation of a L shaped, silicon nitride spacer, on the sides of CMOS logic gate structures, with both silicon nitride shapes defined from the same LPCVD silicon nitride layer. Salicide formation is then initiated in the CMOS logic region, while the silicon nitride blocking shape protects all CMOS memory regions, during the salicide procedure. Prior art, such as Cote et al, in U.S. Pat. No. 4,838,991, as well as Chor et al, in U.S. Pat. No. 5,801,077, describe the use of organic spacers, on the sides of gate structures, however these prior arts do not describe the process sequence for forming silicon nitride, sidewall spacers, for both memory and logic devices, and a salicide blocking shape, for memory devices, from a single deposition of an LPCVD silicon nitride layer.
SUMMARY OF THE INVENTION
It is an object of this invention to integrate the fabrication of CMOS logic devices, featuring salicide layers, with CMOS memory devices, formed without salicide layers.
It is another object of this invention to use only one silicon nitride layer for the formation of silicon nitride spacers, on the sides of the CMOS logic gate structures, and for the formation of a silicon nitride blocking shape, used to prevent salicide formation in the CMOS memory region.
It is still another object of this invention to use an organic spacer, on the sides of all gate structures, as a mask for definition of heavily doped, source/drain regions.
In accordance with the present invention a method of using one silicon nitride for the formation of silicon nitride spacers, on the sides of CMOS logic gate structures, and for the formation of a silicon nitride shape, located in the CMOS memory region, used to prevent salicide formation in the CMOS memory region, is described. After the formation of gate structures, on an underlying gate insulator layer, lightly doped source/drain,(LDD), regions are formed in an area of the semiconductor substrate not covered by the gate structures. After growing a thin silicon oxide layer, on the gate structures, and on the top surfaces of the LDD regions, a first organic layer is deposited, then subjected to an anisotropic reactive ion etch, (RIE), procedure, to create organic spacers, on the sides of the thin silicon oxide coated, gate structures. After creation of heavily doped source/drain regions, in all regions of the semiconductor substrate, not covered by the gate structures, or by the organic spacers, the organic spacer is selectively removed, followed by the deposition of a silicon nitride layer, and of a second organic layer. A photoresist shape is then used to protect the CMOS memory region from another anisotropic RIE procedure, creating a composite spacer, on the sides of the gate structures in the CMOS logic region, with the composite spacer comprised of the overlying, organic shape, and an L shaped, silicon nitride feature. The blanket, anisotropic RIE procedure removes the exposed portions of the silicon nitride layer, in the CMOS logic region, resulting in exposure of the top surface of the gate structure, and the top surface of the heavily doped source/drain region, while all regions of CMOS memory region remain covered by silicon nitride Removal of the photoresist shape, and of all portions of the second organic layer, followed by a hydrofluoric acid procedure, results in a CMOS memory region, still covered with silicon nitride, and a CMOS logic region, still with the silicon nitride component, of the composite spacer, remaining on the sides of the gate structure, however with the top surface of the gate structures, as well as the top surface of the heavily doped source/drain region exposed. Deposition of a metal layer, followed by an anneal procedure, used to form metal silicide on regions in which the metal layer resided on exposed silicon surfaces, followed by removal of unreacted metal, from the surface of the silicon nitride layer, results in the desired salicide formation, in the CMOS logic region only, with silicon nitride spacers on the sides of the CMOS logic gate structures, and the silicon nitride shape, overlying the CMOS memory devices, all accomplished using only one silicon nitride deposition procedure, protecting these regions from salicide formation.
REFERENCES:
patent: 4838991 (1989-06-01), Cote et al.
patent: 5468665 (1995-11-01), Lee et al.
patent: 5747373 (1998-05-01), Yu
patent: 5801077 (1998-09-01), Chor et al.
patent: 5866448 (1999-02-01), Pradeep et al.
patent: 6008077 (1998-12-01), Maeda
patent: 6020242 (2000-02-01), Tsai et al.
patent: 6025267 (2000-02-01), Pey et al.
patent: 6063706 (2000-05-01), Wu
Gerung Henry
Lee Pei Ching
Pradeep Yelehanka Ramachandramurthy
Yu Jie
Chartered Semiconductor Manufacturing Ltd.
Malsawma Lex H.
Pike Rosemary L. S.
Saile George O.
Smith Matthew
LandOfFree
Method of forming a sidewall spacer and a salicide blocking... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a sidewall spacer and a salicide blocking..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a sidewall spacer and a salicide blocking... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2437959