Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-04-06
2009-12-01
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C257S330000, C257S332000, C257SE29201
Reexamination Certificate
active
07625799
ABSTRACT:
A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.
REFERENCES:
patent: 4893160 (1990-01-01), Blanchard
patent: 4941026 (1990-07-01), Temple
patent: 4954854 (1990-09-01), Dhong et al.
patent: 5126807 (1992-06-01), Baba et al.
patent: 5998822 (1999-12-01), Wada et al.
patent: 6174773 (2001-01-01), Fujishima
patent: 6337499 (2002-01-01), Werner
patent: 6376878 (2002-04-01), Kocon
patent: 6586800 (2003-07-01), Brown
patent: 6683346 (2004-01-01), Zeng
patent: 6690062 (2004-02-01), Henninger et al.
patent: 6750508 (2004-06-01), Omura et al.
patent: 6803626 (2004-10-01), Sapp et al.
patent: 7393749 (2008-07-01), Yilmaz et al.
patent: 7504303 (2009-03-01), Yilmaz
patent: 7514322 (2009-04-01), Yilmaz et al.
patent: 2005/0062102 (2005-03-01), Dudek et al.
patent: 2005/0062105 (2005-03-01), Nakamura et al.
patent: 2005/0151190 (2005-07-01), Kotek et al.
patent: 2005/0167742 (2005-08-01), Challa et al.
patent: 2005/0181564 (2005-08-01), Hshieh et al.
patent: 2006/0267088 (2006-11-01), Sharp et al.
patent: 2006/0273386 (2006-12-01), Yilmaz
patent: 504290 (2008-04-01), None
patent: 112006001516 (2008-04-01), None
patent: 2008-546216 (2008-12-01), None
patent: WO 01/88997 (2001-11-01), None
patent: WO 2006/135746 (2006-12-01), None
International Search Report of the International Searching Authority for Application No. PCT/US2006/022474, Mailed Jan. 14, 2008, 3 pages.
Written Opinion of the International Searching Authority for Application No. PCT/US2006/022474, mailed Jan. 14, 2008, 6 pages.
Notice of Allowance for U.S. Appl. No. 11/450,903, Mailed Apr. 4, 2008, 9 pages.
Japanese Office Action for Application No. 2008-515966, Jul. 8, 2008, 3 pages.
Notice of Allowance for U.S. Appl. No. 12/125,242, Mailed Sep. 19, 2008, 6 pages.
Notice of Allowance for U.S. Appl. No. 12/125,242, Mailed Nov. 28, 2008, 8 pages.
International Preliminary Report on Patentability for Application No. PCT/US2006/022474, mailed Mar. 31, 2009, 7 pages.
Calafut Daniel
Challa Ashok
Kraft Nathan
Sapp Steven
Yilmaz Hamza
Fairchild Semiconductor Corporation
Pham Thanh V
Townsend and Townsend / and Crew LLP
LandOfFree
Method of forming a shielded gate field effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a shielded gate field effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a shielded gate field effect transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4090994