Method of forming a semiconductor structure having reduced thres

Details Method of forming a semiconductor structure having reduced thres Method of forming a semiconductor structure having reduced thres

1997-07-11

1999-05-25

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438273, 438589, H01L 21336

Patent

active

059077760

ABSTRACT:
A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device formed on a semiconductor substrate having a body region of a first conductivity type diffused in a semiconductor substrate with an epitaxial layer of a second conductivity type. There is also a source region of a second conductivity type formed in the body region. A portion of the body region adjacent to the source region is compensated by ion implanting a material of the second conductivity type in the portion of the body region such that the impurity concentration of the body region at the portion is reduced. As a consequence, with reduced impurity charge in the body region adjacent to the source, the threshold voltage of the MOSFET device is lowered but at no comprise in punch-through tolerance because the reduction in charge is remote from the origin of the depletion layer which is located at the boundary between the body region and the epitaxial layer.

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patent: 5527720 (1996-06-01), Goodyear et al.
patent: 5567634 (1996-10-01), Hebert et al.
patent: 5648288 (1997-07-01), Williams et al.

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