Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-28
2001-05-15
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000
Reexamination Certificate
active
06232163
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit chips and more particularly to electrostatic discharge protect devices for integrated circuit chips.
2. Background Description
As semiconductor device features are shrunk with each new technology generation, device insulating layers are thinned proportionately, i.e., “scaling”. These thinner dielectric layers fail at lower voltages. Consequently, polysilicon gate structure scaling increases circuit sensitivity to voltage stress, electrical overstress (EOS) and electrostatic discharge (ESD) failures. These types of failures are a major concern in insulated gate field effect transistor (FET) technologies, typically referred to as MOSFET. This is especially true for MOSFET chips that interface to other chips or signals with voltages above that of the MOSFET chip itself.
FIGS. 1A-B
, are cross-sectional views of a prior art protect device structures
100
,
102
. Each device includes a gate
104
insulated from a semiconductor body
106
by an insulator layer
108
.
In
FIG. 1A
, the device
100
is a lightly doped drain (LDD) field effect transistor diode with a p-type diffusion
110
on one side of the gate
104
and an n-type diffusion
112
is on the opposite side. Nitride spacers
114
over lightly doped regions (not shown) on each side of the gate
104
, insure that the edges of the gate
104
are spaced away from diffusions
110
and
112
. Shallow trench isolation (STI)
116
is provided at each diffusion
110
,
112
to isolate the diode
100
from adjacent circuits.
In
FIG. 1B
a p-type diffusion
110
is on one side of and adjacent to the gate
104
and shallow trench isolation
118
separates the gate from n-type diffusion
112
. In both of these prior art devices, the gate
104
is either n-type or p-type polysilicon.
Normally, integrated circuit (IC) chips include protect devices or diodes such as those in
FIGS. 1A
or
1
B in interface circuits to provide the IC chip with added ESD protection. U.S. Pat. No. 5,629,544, entitled “Semiconductor Diode with Silicide Films and Trench Isolation” to Voldman et al. teaches using diode structures bound by polysilicon for bulk silicon and silicon on insulator (SOI) MOSFET applications. However, where MOSFET chips must interface with higher voltage signals or, chips operating at voltages above the MOSFET's native voltage, these polysilicon protect devices do not provide adequate protection. ESD type failures are the result of this inadequate protection.
Further, on some SOI chips ESD protection is provided by a lateral unidirectional bipolar type insulated gate transistor known as a Lubistor. Lubistors are also sensitive to the dielectric stress.
Thus, there is a need for thin oxide diodes that are less sensitive to dielectric failures from electric field stress.
SUMMARY OF THE INVENTION
It is therefore a purpose of the present invention to reduce integrated circuit chip dielectric field stress failures.
It is another purpose of the present invention to improve MOSFET circuit ESD protection.
It is yet another purpose of the present invention to improve SOI chip ESD protection.
The present invention is a high voltage tolerant diode structure that may be used in mixed-voltage, and mixed signal and analog/digital applications. The preferred diode includes a low doped polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. The polysilicon diode is in a film shorted at one surface by a conducting layer or cap. As voltage is applied to the polysilicon film, it electrically depletes reducing the voltage stress across the dielectric film. This depletable film is achieved by counter-doping the polysilicon or, by a low doped implantation of the polysilicon film. In one embodiment, a low doped source/drain implant is used to establish the polysilicon film dopant concentration. In another embodiment, a low doped MOSFET LDD or extension implant is used to establish the polysilicon gate dopant concentration. In yet another embodiment, a block mask is formed over the gate structure when defining the depleted polysilicon diode to form low series resistance diode implants, thereby preventing over-doping the gate structure. In an alternate embodiment, a higher doped edge implant is defined in the structure in silicon at a spacer edge using a hybrid photoresist method to increase the dopant concentration on the edge implants, reducing diode series resistance without using a block mask. The preferred diode structure is formed on a well or an implanted area in a bulk semiconductor substrate.
In another embodiment the diode structure is a lateral unidirectional bipolar insulated gate type transistor (Lubistor) on a silicon-on-insulator (SOI) wafer. The preferred Lubistor is defined using a well implant of a surface silicon layer. A dielectric film is buried in the supporting silicon substrate.
Polysilicon depletion for preferred embodiment diode exhibit a unique capacitance—voltage (C-V) characteristic, with a unique voltage dependency for both preferred diodes and Lubistor structures. The polysilicon depletion may be used for both voltage stress reduction and in circuit applications, such as in diode-based ESD networks.
REFERENCES:
patent: 4492974 (1985-01-01), Yoshida et al.
patent: 4516223 (1985-05-01), Erickson
patent: 4616404 (1986-10-01), Wang et al.
patent: 4714519 (1987-12-01), Pfiester
patent: 4760433 (1988-07-01), Young et al.
patent: 4760434 (1988-07-01), Tsuzuki et al.
patent: 4896199 (1990-01-01), Tsuzuki et al.
patent: 5128731 (1992-07-01), Lien et al.
patent: 5136348 (1992-08-01), Tsuzuki et al.
patent: 5227655 (1993-07-01), Kayama
patent: 5365099 (1994-11-01), Phipps et al.
patent: 5438007 (1995-08-01), Vinal et al.
patent: 5449937 (1995-09-01), Arimura et al.
patent: 5502338 (1996-03-01), Suda et al.
patent: 5543642 (1996-08-01), Byrne
patent: 5589415 (1996-12-01), Blanchard
patent: 5602046 (1997-02-01), Calafut et al.
patent: 5602404 (1997-02-01), Chen et al.
patent: 5629544 (1997-05-01), Voldman et al.
patent: 5631187 (1997-05-01), Phipps et al.
patent: 5661069 (1997-08-01), Owens et al.
patent: 5841172 (1998-11-01), Morishita et al.
patent: 5977591 (1999-11-01), Fratin
patent: 401185971 (1989-07-01), None
Brown Jeffrey S.
Gauthier Jr. Robert J.
Voldman Steven H.
Chaudhuri Olik
International Business Machines - Corporation
McGuireWoods LLP
Pham Hoai
Shkurko, Esq. Eugene I.
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