Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-06
2001-07-31
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S682000, C438S664000
Reexamination Certificate
active
06268255
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of forming metal silicide regions on a semiconductor device, and a device comprising the same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. By way of background,
FIG. 1
depicts an illustrative NMOS field effect transistor
10
formed above a surface
14
of a semiconducting substrate
12
between trench isolation regions
25
. The transistor
10
is comprised of a gate dielectric
16
, a gate electrode
18
, a plurality of sidewall spacers
20
and multiple source/drain regions
28
. The transistor
10
is further comprised of metal silicide contacts
21
formed on the source/drain regions
28
and on the gate electrode
18
.
The aforementioned demand for increased operating speed of integrated circuit devices has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, the size of many components of a typical field effect transistor, e.g., channel length, source/drain junction depths, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
As the channel length has been reduced to obtain the desired switching characteristic, the length of the gate electrode has also been reduced. Since the gate electrode may only be electrically connected at one end, the electrical charges used to establish a transverse electrical field for forming the channel between the drain region and the source region of the transistor have to be transported along the entire width of the gate electrode. Given the small transverse dimension (length) of the gate electrode, the electrical resistance is relatively high, which may result in higher RC-delay time-constants. Hence, generation of the transverse electrical field used to fully open the channel is delayed, thereby deteriorating the switching time of the transistor. As a consequence, the rise and fall times of the electrical signals are increased and the operating frequency, i.e., the clock frequency, is reduced. Thus, the switching time of the transistor is no longer limited by the drain and source characteristics, but rather significantly depends on the delay associated with signal propagation along the gate electrode, i.e., the transistor performance depends, at least in part, on the resistance of the gate electrode in the longitudinal direction of the gate electrode, i.e., in the gate width direction.
The reduction in the channel length of modern semiconductor devices also requires a reduction in the depth of the source and drain regions adjacent the gate electrode. This may be problematic when the source/drain regions are subjected to a salicidation process. In general, salicidation involves the process of forming a layer of refractory metal, e.g., cobalt, titanium, above a structure comprised of silicon, e.g., a polysilicon gate electrode and/or the source/drain regions of a transistor device, and, thereafter, subjecting the device to an anneal process, typically a two-step anneal process, such that a metal silicide, e.g., cobalt silicide or titanium silicide, is formed where the refractory metal is exposed to silicon. The purpose of the salicidation process is to, among other things, reduce the resistance of the components subject to the salicidation process. Thereafter, the unreacted portions of the refractory metal layer are removed. The purpose of the salicidation process is to, among other things, reduce the resistance of the components subject to the salicidation process.
However, traditional salicidation processes have become problematic with modern semiconductor devices that have shallow source/drain junctions, e.g., junction depths on the order of 1000 Å or less. In particular, during such salicidation processes, some of the existing source/drain regions are consumed. For example, when cobalt is used as the refractory metal, it consumes about twice its thickness of silicon in the process of being converted to a metal silicide, e.g., a 100 Å layer of cobalt consumes about 103 Å of silicon. Such consumption acts to reduce the dopant present in the source/drain regions and may adversely impact the electrical performance characteristics of the source/drain regions, and ultimately, the performance of the integrated circuit device. Given the fact that source/drain regions in modern semiconductor devices are already made very shallow, further reductions in the depth of these regions is undesirable.
The present invention is directed to a semiconductor device that minimizes or reduces some or all of the aforementioned problems and a method of making same.
SUMMARY OF THE INVENTION
The present invention is directed to a method of forming a semiconductor device having metal silicide regions formed thereon. In one illustrative embodiment, the method comprises forming a first layer comprised of polysilicon, forming a second layer comprised of a refractory metal above the layer of polysilicon and converting at least a portion of the second layer to a first metal silicide. The method further comprises forming an anti-reflective coating layer above the layer of refractory metal or the first metal silicide layer, and patterning the first metal silicide layer and the layer of polysilicon to define a gate stack comprised of a first metal silicide region and a layer of polysilicon. The method also comprises forming a plurality of source/drain regions in the substrate, forming a third layer comprised of a refractory metal above at least the gate stack and the source/drain regions, and converting at least a portion of the third layer to a second metal silicide region.
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Goto et al., “Optimization of Salicide Processes for sub 0.1-&mgr;m CMOS Devices,”1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 119-120, Apr. 1994.
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Besser Paul R.
Kepler Nicholas J.
Zistl Christian
Advanced Micro Devices , Inc.
Lindsay Jr. Walter L.
Niebling John F.
Williams Morgan & Amerson P.C.
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