Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-29
2002-08-27
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S420000, C438S528000
Reexamination Certificate
active
06440805
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to the field of semiconductor fabrication and more particularly to a method and structure for reducing soft error rate in a semiconductor circuit.
RELATED ART
Semiconductor memory products are susceptible to a data loss phenomenon generally referred to as soft errors. Soft errors in semiconductor products may result from environmental radiation that alters the amount of charge stored on a semiconductor circuit such as a static random access memory (SRAM) or dynamic random access memory (DRAM) device. In many integrated circuits including SRAMs and DRAMs, the logical state of the integrated circuit is dependent upon an extremely small amount of stored charge. Environmental particle radiation originating from a variety of sources can alter the amount of charge stored in a cell or element of a memory device. It will be appreciated that the soft error rate varies with the amount of charge stored on a storage node of the memory device. As the power supply voltage and the cell size of memory devices decrease, the amount of charge stored decreases accordingly thereby increasing the probability of a soft error event. Therefore, it would be highly desirable to implement a process and device that could substantially reduce the soft error rate without significantly increasing the cost or complexity of the process.
REFERENCES:
patent: 5286666 (1994-02-01), Katto et al.
patent: 5394007 (1995-02-01), Reuss et al.
patent: 5397734 (1995-03-01), Iguchi et al.
patent: 5455437 (1995-10-01), Komori et al.
patent: 5585286 (1996-12-01), Aronowitz et al.
patent: 5668755 (1997-09-01), Hidaka
patent: 5780907 (1998-07-01), Ema et al.
patent: 5927991 (1999-07-01), Lee
patent: 6221724 (2001-04-01), Yu et al.
patent: 6225151 (2001-05-01), Gardner et al.
patent: 0809302 (1997-11-01), None
patent: WO 86/02202 (1986-04-01), None
Tamohisa Wada et al., “A 500MHz Pipelined Burst SRAM with Improved SER Immunity”, ISSCC99, 1999 IEEE International Solid State Cir. Conf., Session 11, Paper TA 11.4, pp. 196-197.
Craig Lage et al., “Soft Error Rate and Stored Charge Requirement in Advanced High-Density SRAMs”, 1993 IEEE International Electron Device Mtg., pgs.
Tomohisa Wada et al., “A 500MHz Pipelined Burst SRAM with Improved SER Immunity”, 1999 IEEE International Aolid-State Circuits Conference, pp. 196-197.
PCT Search Report, PCT/US 01/03115 (3 pgs.).
Lage Craig S.
Tian Hong
Wang Xiaodong
Woo Michael P.
Chaudhari Chandra
Lally Joseph P.
Mototrola, Inc.
Rodriguez Robert A.
LandOfFree
Method of forming a semiconductor device with isolation and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a semiconductor device with isolation and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a semiconductor device with isolation and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2963056