Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-11-20
2003-04-15
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S692000
Reexamination Certificate
active
06548399
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods for making semiconductor devices, in particular, those that apply a chemical mechanical polishing process to planarize a dielectric layer.
BACKGROUND OF THE INVENTION
When making semiconductor devices, dielectric layers are used to separate various components (e.g., transistors and capacitors) from each other or from conductive layers formed on top of them. Such dielectric layers may also separate conductive layers (or other structures or elements) from each other. When initially formed, a dielectric layer may assume a shape that conforms to the underlying topography. If that layer is formed on a surface that has raised and recessed features, then it can likewise have elevated and recessed sections.
It may be desirable to planarize such a dielectric layer prior to forming subsequent layers on its surface. A chemical mechanical polishing (“CMP”) process may be used to planarize such a layer. To achieve that result, it may be necessary to control such a CMP process to cause it to remove more material where the dielectric layer is elevated, and less material where the dielectric layer is recessed. By removing different amounts of material from different sections of the dielectric layer, a CMP process can planarize a dielectric layer, which had an irregular topography when deposited.
Some processes require a dielectric layer to be planarized, not to produce a substantially flat layer that covers an entire wafer, but instead to generate a structure in which a dielectric layer fills a trench. To make such a structure, a trench is formed within a substrate, or between raised members, followed by depositing a dielectric material over the resulting structure. A CMP process may then be used to remove the deposited material, except where it fills the trench. Measures often must be taken to prevent that process from removing too much of the dielectric layer from the trench, or from removing portions of other materials that should be retained.
To control the CMP process, when used in such a method, it may be necessary to limit its duration, or to form a polish stop layer below the dielectric material. A silicon nitride layer may serve as such a polish stop layer when, for example, forming a shallow trench isolation region in a substrate, which will separate devices to be formed on adjacent active regions. Such a polish stop layer prevents a CMP process from removing an excessive amount of the dielectric material (e.g., silicon dioxide) from the trench, while protecting other portions of the substrate.
Current methods for controlling the CMP process, when used to planarize a dielectric layer, may not be especially robust. In particular, using silicon nitride as a polish stop layer can be problematic, if the polish rate selectivity for the dielectric layer to the silicon nitride layer is about 4:1 or less. Because, in general, CMP processes are inherently nonuniform, such a polish rate selectivity may require forming a thicker silicon nitride layer than would otherwise be desired. A thicker layer may be necessary to prevent the CMP process from having to break through parts of it to ensure the complete removal of the dielectric layer that is deposited on the silicon nitride layer's surface. Integrating a thicker silicon nitride layer into the process may decrease throughput, as it takes longer to deposit and etch a thicker layer. In addition, forming a thicker layer will increase the aspect ratio (i.e., the ratio of height to width) of the trench, which could make it more difficult to fill the trench with the dielectric layer.
Accordingly, there is a need for an improved method for controlling a CMP process that is used to remove portions of a dielectric material, when making a semiconductor device. There is a need for such a method that provides an improved polish stop layer for terminating a CMP process after it has removed the dielectric material from the polish stop layer's surface. There is also a need for such a method that enables a CMP process to effectively planarize a dielectric layer, which has an uneven topography when initially formed. The process of the present invention provides such a method.
REFERENCES:
patent: 5688720 (1997-11-01), Hayashi
patent: 5719085 (1998-02-01), Moon et al.
patent: 5721172 (1998-02-01), Jang et al.
patent: 5872043 (1999-02-01), Chen
patent: 6025273 (2000-02-01), Chen et al.
patent: 6030892 (2000-02-01), Wu et al.
patent: 6051496 (2000-04-01), Jang
patent: 6127259 (2000-10-01), Shields et al.
patent: 6316063 (2001-11-01), Andideh et al.
patent: 6348421 (2002-02-01), Shu et al.
patent: 6383935 (2002-05-01), Lin et al.
patent: 6384482 (2002-05-01), Yang et al.
patent: 6391783 (2002-05-01), Sudijono et al.
patent: 6436822 (2002-08-01), Towle
patent: 6482754 (2002-11-01), Andideh et al.
patent: 2002/0031985 (2002-03-01), Wang et al.
patent: 2002/0068436 (2002-06-01), Dakshina-Murthy et al.
Andideh Ebrahim
Cummins Clark
Blum David S
Intel Corporation
Jr. Carl Whitehead
Seeley Mark V.
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