Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-19
2003-04-08
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000
Reexamination Certificate
active
06544834
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a technique for manufacturing such device, and, more particularly, to a technique that is effectively applied to a semiconductor device having a DRAM (Dynamic Random Access Memory).
BACKGROUND OF ART
A plurality of word lines and a plurality of bit lines are arranged in a matrix shape on a main surface of a semiconductor substrate. Memory cells of a DRAM are located at respective intersections where both lines meet. Each of the memory cells comprises a memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and an information storage capacity element (capacitor) connected thereto in a series. The memory cell selection MISFET is formed in an active region surrounded by an element isolation region. The memory cell selection MISFET mainly comprises a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions having a source and a drain. The bit lines are arranged above the memory cell selection MISFETs, respectively, and electrically connected to one of the source and the drain that are shared with two adjacent memory cell selection MISFETs in a direction extended along the bit lines. The information storage capacity element is also located above the memory cell selection MISFET and electrically connected to the other of the source and the drain.
Japanese Patent Application Laid-open No. 7-7084 discloses a DRAM having a Capacitor Over Bitline structure where an information storage capacity element is arranged above a bit line. In such disclosed DRAM, in order to compensate for a decreasing amount of storage electric charge (Cs) of the information storage capacity element due to fineness of the memory cell, an surface area thereof is increased by forming, in a cylindrical shape, a lower electrode (a storage electrode) of the information storage capacity element located above the bit line, and a capacity insulation film and an upper electrode (a plate electrode) are formed thereabove. As the capacity insulation film, a stack insulation film formed by both silicon oxide film and silicon nitride film is used.
However, as the DRAM develops in both high integration and fineness, the surface area of the lower electrode is reduced. Therefore, the capacity insulation film comprising the stack insulation film formed by both silicon oxide and silicon nitride films, has difficulty securing enough amount of storage electric charge. Meanwhile, if film thickness of the capacity insulation film is reduced to secure enough amount of storage electric charge, leak current between the upper electrode and the lower electrode is increased so that refresh characteristics (reliability) of the DRAM is increased. Accordingly, means are needed in which a necessary amount of the storage electric charge is secured even in a capacity insulation film having enough film thickness to restrict generation of the leak current, and various methods for performing the means are proposed.
One of the methods is a method for using the capacity insulation film made of a highly dielectric or ferroelectric material, thinning the film thickness of the capacity insulation film effective in case where the capacity insulation film is converted into the silicon oxide film, and securing enough capacity value. A tantalum oxide film is typically used as such an insulating film. Technologies for using the tantalum oxide film as a capacity insulating film are described in pages 853-855 and 862-864 of “Extended Abstracts of the 1993 International Conference on Solid State Device and Materials, Makuhari”, or in page 728 of “Abstracts of the 43rd Associated Exhibition for Applied Physics”, or the like.
Further, since tantalum oxide film is generally formed by means of CVD method using organic tantalum gas, it is difficult to form the tantalum oxide film by deposition at high temperature. Therefore, the tantalum oxide film being in an as-deposited state is in an amorphous state, so that it is necessary to crystallize it after being treated thermally in order to obtain a capacity insulation film having a high permittivity. On the other hand, methods have been proposed which reform the tantalum oxide film by heat or plasma treatment under an oxidizing atmosphere of about 400° C. for avoiding heat treatment under high temperature.
However, the tantalum oxide film reformed by heat or plasma treatment is not crystallized and remains in an amorphous state. If being used as a capacity insulating film, the amorphous tantalum oxide film can not have a high permittivity. And, non-crystallized tantalum oxide film is degraded in film quality by heat treatment (performed, for example, at between 400 and 600° C.) or the like for obtaining electrical conduction of connecting portions between distributing wires provided after an information storage capacity element is formed and another distributing wires or substrate provided below the distributing wires. Therefore there is the drawback that reliability of the DRAM is decreased because of, for example, increase of leak current generated in the capacity insulation film or the like.
On the other hand, the tantalum oxide film being in an amorphous state requires heat treatment at more than 750° C. for crystallization thereof if an underlying layer thereof is made of silicon, oxide or nitride of the silicon, or the like. While the crystallized tantalum oxide film does not give rise to any degradation in film quality if being subjected to heat treatment thereafter, the following problems arise when the DRAM has a COB structure.
In the DRAM having the COB structure, before an information storage capacity element is formed, bit lines are provided together with first distributing wires layer in a peripheral circuit formed on the same layer that the bit lines are arranged on. A connecting part between the first distributing wires layer in this peripheral circuit region and the semiconductor substrate is normally provided with a metal silicide film in order to reduce a connecting resistance. If the DRAM having such structure is heat-treated at more than 750° C. as described above, the metal silicide film of said connecting part is affected by the heat treatment to raise the connecting resistance. Thereby, in the worst case, there is a problem of destruction of the metal silicide film.
Additionally, whether being crystallized or not, the tantalum oxide film has to be treated in an oxidizing atmosphere. Oxidization of the underlying substrate under such oxidation treatment causes the following problems. That is, if lower electrodes which are underlying are made of silicon, silicon oxide film is formed between the lower electrodes and the tantalum oxide film, film thickness of capacity insulation film is effectively increased because of insulator films having lower permittivity in the tantalum oxide film. Thereby, the capacity insulation element can not have enough capacitance value to be desired. On the other hand, if the lower electrodes which are underlying are made of metal such as titanium nitride, tungsten or the like, a case where the oxide is an insulator film causes increase of the capacity insulator film in film thickness as described above, too. Or, a case where the oxide is formed by electric conductor materials causes cubic expansion due to formation of the metal oxide, and increases leak current in the tantalum oxide film because of stress influencing the tantalum oxide film.
An object of the present invention is to provide a capacity insulation film that has both high heat resistance and reliability and that can increase an amount of storage electric charge thereof.
And, an object of the present invention is to provide a technique for crystallizing the tantalum oxide film by heat treatment at low temperature, without degrading the metal silicide film of the connecting part for distributing wires.
And, an object of the present invention is to provide a technique for suppressing oxidation of the underlying substrate when the tantalum oxide film is crys
Hiratani Masahiko
Iijima Shinpei
Kanai Misuzu
Nakanishi Naruhiko
Oji Yuzuru
Antonelli Terry Stout & Kraus LLP
Brewster William M.
Chaudhuri Olik
Hitachi , Ltd.
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