Method of forming a semiconductor device having a stacked capaci

Details Method of forming a semiconductor device having a stacked capaci Method of forming a semiconductor device having a stacked capaci

1998-04-22

1999-12-07

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 218242

Patent

active

059982586

ABSTRACT:
The present invention is a process for forming a lower capacitor electrode. Specifically, an oxygen tolerant bottom electrode layer (312) is formed over a conductive plug (216). A dielectric layer (420) is deposited and partially removed in order to form an inlaid bottom electrode structure. A capacitor dielectric (810) such as BST is formed over the lower electrode (310). The upper electrode (812) is formed over the capacitor dielectric (810) and the resulting stack is patterned in order to form a final capacitive device (916). In another embodiment of the present invention, a hardmask is formed over the bottom electrode (310) and removed prior to the capacitor dielectric (810) being formed.

REFERENCES:
patent: 5285092 (1994-02-01), Yoneda
patent: 5381302 (1995-01-01), Sandhu et al.
patent: 5510651 (1996-04-01), Maniar et al.
patent: 5559047 (1996-09-01), Urabe
patent: 5668041 (1997-09-01), Okudaira et al.
patent: 5717250 (1998-02-01), Schuele et al.
Kohyama et al., "A fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyond," 1997 Symposium on VLSI Technology Digest of Technical Papers. pp. 17-18.
Kim et al., "Highly Manufacturable 1Gb SDRAM," 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 9-10.

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